Abstract: Disclosed herein is a data processing apparatus and method. The data processing apparatus includes a terminal communication unit. A first control unit extracts a command packet based on a command block wrapper packet. A first unit-side communication unit transmits the command packet to a second unit. When the first unit-side communication unit receives a data status packet, generated based on one or more data packets responding to the command packet, from the second unit, the first control unit extracts a data packet from the data status packet in response to a packet for a data transmission request of a host terminal, and wherein the terminal communication unit transmits the data packet extracted from the data status packet to the host terminal.

Abstract: Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.

Abstract: Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.

Abstract: Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.