Patents by Inventor Chi-Hsien Chung

Chi-Hsien Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072090
    Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.
    Type: Application
    Filed: January 5, 2023
    Publication date: February 29, 2024
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Tzu-Hsuan Hsu, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240014245
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.
    Type: Application
    Filed: January 4, 2023
    Publication date: January 11, 2024
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Shang-Fu Yeh, Tzu-Hsuan Hsu, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20230411431
    Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).
    Type: Application
    Filed: August 15, 2022
    Publication date: December 21, 2023
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Chen-Jong Wang, Tzu-Hsuan Hsu, Dun-Nian Yaung
  • Publication number: 20230299109
    Abstract: A semiconductor device includes a first chip comprising a plurality of photo-sensitive devices, wherein the plurality of photo-sensitive devices are formed as a first array. The semiconductor device includes a second chip bonded to the first chip and comprising: a plurality of groups of pixel transistors, wherein the plurality of groups of pixel transistors are formed as a second array; and a plurality of input/output transistors, wherein the plurality of input/output transistors are disposed outside the second array. The semiconductor device includes a third chip bonded to the second chip and comprising a plurality of logic transistors.
    Type: Application
    Filed: June 27, 2022
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Chen-Jong Wang, Tzu-Hsuan Hsu, Dun-Nian Yaung, Calvin Yi-Ping Chao
  • Patent number: 8537207
    Abstract: A video-audio playing system relating to 2-view application and a method thereof are provided. In the present invention, sound signals respectively corresponding to two independent image frames are captured and played in coordinating with the displaying of these two independent image frames. Accordingly, two users can respectively watch two image frames which are different and irrelevant each other in the same display, and further respectively hear sound effects of the respective image frames at the same time.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 17, 2013
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chang Shih, Yang-Ching Cheng, Sheng-Ju Ho, Chi-Hsien Chung, Wan-Ting Chen, Cheng-Han Tsao
  • Publication number: 20120281144
    Abstract: A video-audio playing system relating to 2-view application and a method thereof are provided. In the present invention, sound signals respectively corresponding to two independent image frames are captured and played in coordinating with the displaying of these two independent image frames. Accordingly, two users can respectively watch two image frames which are different and irrelevant each other in the same display, and further respectively hear sound effects of the respective image frames at the same time.
    Type: Application
    Filed: October 4, 2011
    Publication date: November 8, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Chang Shih, Yang-Ching Cheng, Sheng-Ju Ho, Chi-Hsien Chung, Wan-Ting Chen, Cheng-Han Tsao