Abstract: A polar transmitter includes: a processor arranged to convert signals from a specific coordinate system to a polar coordinate system, wherein the signals in the polar coordinate system comprises a phase component and an amplitude component; a phase modulation (PM) path configured to have a constant PM group delay, for processing the phase component; an amplitude modulation (AM) path, of which an AM group delay is capable of being determined, for processing the amplitude component; and an adjustable delay circuit, arranged to adjust delay of the signals in the specific coordinate system according to the constant PM group delay and the calibrated AM group delay.

Abstract: Wireless receiver for receiving a plurality of co-existing wireless signals respectively from different positioning systems, includes an analog frontend and an analog-to-digital converting unit. The analog frontend is arranged to convert bands of the co-existing wireless signals into a plurality of corresponding intermediate bands by a local frequency and to provide an intermediate signal including the intermediate bands. The analog-to-digital converting unit is coupled to the analog frontend, and is arranged to convert the intermediate signal to a digital signal, wherein an operation band of the analog-to-digital converting unit covers the plurality of intermediate bands.

Abstract: A polar transmitter includes: a processor arranged to convert signals from a specific coordinate system to a polar coordinate system, wherein the signals in the polar coordinate system comprises a phase component and an amplitude component; a PM path configured to have a constant PM group delay, for processing the phase component; an AM path, of which an AM group delay is capable of being determined, for processing the amplitude component; and an adjustable delay circuit, arranged to adjust delay of the signals in the specific coordinate system according to the constant PM group delay and the calibrated AM group delay.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.

Abstract: One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.