Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.

Abstract: The present disclosure provides a molding system for fabricating a FRP composite article. The molding system includes a detector, a resin dispenser, a processing module, and a molding machine. The detector is configured to capture a graph of a woven fiber from a top view. The resin dispenser is configured to provide a resin to the woven fiber to form a FRP. The processing module is configured to receive the graph and a plurality of parameters of the FRP. The processing module includes a CNN model, and is configured to use the CNN model to obtain a plurality of predicted mechanical properties of the FRP according to the graph and the plurality of parameters of the FRP. The molding machine is configured to mold the FRP to fabricate the FRP composite article according to the plurality of predicted mechanical properties.

Abstract: A method for fabricating a semiconductor device is provided and includes the following steps: providing a substrate; forming a lower electrode on the substrate; forming at least one sub-dielectric layer on the lower electrode; patterning the dielectric layer to form an intermediate dielectric layer, where the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; forming a hole by etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer; filling at least one plug into the hole; and forming an upper electrode on the intermediate dielectric layer.

Abstract: Materials-by-design is a new paradigm to develop novel high-performance materials. However, finding materials with superior properties is often computationally or experimentally intractable because of the astronomical number of combinations in design spaces. The disclosure is a novel AI-based approach, implemented in a game-theory based generative adversarial neural network (GAN), to bridge the gap between the physical performance and design space. A end-to-end deep learning model predicts physical fields like stress or strain directly from the material geometry and microstructure. The model reaches an astonishing accuracy not only for predicted field data but also for secondary predictions, such as average residual stress at R2˜0.96). Furthermore, the proposed approach offers extensibility by predicting complex materials behavior regardless of shapes, boundary conditions and geometrical hierarchy.

Abstract: A method for fabricating a semiconductor device is provided and includes the following steps: providing a substrate; forming a lower electrode on the substrate; forming at least one sub-dielectric layer on the lower electrode; patterning the dielectric layer to form an intermediate dielectric layer, where the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; forming a hole by etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer; filling at least one plug into the hole; and forming an upper electrode on the intermediate dielectric layer.

Abstract: A semiconductor device includes a substrate, a capacitor disposed on the substrate, and an interconnection structure. The capacitor is disposed on the substrate within a capacitor region and includes a lower electrode, an upper electrode, a stacked dielectric layer, and an intermediate dielectric layer. The upper electrode is disposed over the lower electrode, and the stacked dielectric layer is disposed between the lower electrode and the upper electrode. The intermediate dielectric layer is disposed between the lower electrode and the upper electrode and disposed only within the capacitor region. The relative permittivity of the intermediate dielectric layer is greater than the relative permittivity of the stacked dielectric layer. The interconnection structure including a plug and a stack of metal layers is disposed within an interconnection region abutting the capacitor region and is disposed at at least one side of the intermediate dielectric layer.

Abstract: A semiconductor device includes a substrate, a capacitor disposed on the substrate, and an interconnection structure. The capacitor is disposed on the substrate within a capacitor region and includes a lower electrode, an upper electrode, a stacked dielectric layer, and an intermediate dielectric layer. The upper electrode is disposed over the lower electrode, and the stacked dielectric layer is disposed between the lower electrode and the upper electrode. The intermediate dielectric layer is disposed between the lower electrode and the upper electrode and disposed only within the capacitor region. The relative permittivity of the intermediate dielectric layer is greater than the relative permittivity of the stacked dielectric layer. The interconnection structure including a plug and a stack of metal layers is disposed within an interconnection region abutting the capacitor region and is disposed at at least one side of the intermediate dielectric layer.

Abstract: An illumination device includes a base, a flexible circuit board disposed on the base, and a plurality of illumination units. The flexible circuit board has a plurality of first branches and at least one second branch which are connected together. Each of the first branches has a radius of curvature, and the radii of curvature of the first branches are different from or identical to one another, so that the first branches are assembled to form a curved surface. The second branch extends from one of the first branches. After the first branches are assembled, the second branch is overlapped with another first branch. The illumination units are packaged onto the first branches of the flexible circuit board. Here, the illumination units located on one of the first branches is electrically connected to the illumination units located on another of the first branches through the second branch.

Abstract: A planting container is suitable for forming planting columns by using ones with the same structure three-dimensionally stacked. The planting columns are arranged around a center line parallel to the gravity direction to set up a planting tower. The planting container includes a bottom wall and a side wall. The side wall extends from the peripheral of the bottom wall and both walls define a containing space. The side wall has a planting opening communicating with the containing space. The side wall has a top end and a bottom end. When two containers with the same structure are three-dimensionally stacked by each other, the bottom end of the upper container engages with the top end of the lower container. The side wall laterally tilts towards the center line relatively to the bottom wall, so that the planting column tilts towards the adjacent column and tilts towards the center line.

Abstract: A planting container is suitable for forming planting columns by using ones with the same structure three-dimensionally stacked. The planting columns are arranged around a center line parallel to the gravity direction to set up a planting tower. The planting container includes a bottom wall and a side wall. The side wall extends from the peripheral of the bottom wall and both walls define a containing space. The side wall has a planting opening communicating with the containing space. The side wall has a top end and a bottom end. When two containers with the same structure are three-dimensionally stacked by each other, the bottom end of the upper container engages with the top end of the lower container. The side wall laterally tilts towards the center line relatively to the bottom wall, so that the planting column tilts towards the adjacent column and tilts towards the center line.

Abstract: A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The second thermal member forms a plurality of through holes for heat dissipation. The light source is disposed on the second thermal member, and the connecting member connects the thermal module with the adapter.

Abstract: An illumination device includes a base, a flexible circuit board disposed on the base, and a plurality of illumination units. The flexible circuit board has a plurality of first branches and at least one second branch which are connected together. Each of the first branches has a radius of curvature, and the radii of curvature of the first branches are different from or identical to one another, so that the first branches are assembled to form a curved surface. The second branch extends from one of the first branches. After the first branches are assembled, the second branch is overlapped with another first branch. The illumination units are packaged onto the first branches of the flexible circuit board. Here, the illumination units located on one of the first branches is electrically connected to the illumination units located on another of the first branches through the second branch.

Abstract: A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member which are formed by a die casting process, wherein the light source is disposed on the second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The connecting member is formed by a metal extrusion process and extends through the first thermal member to connect the second thermal member with the adapter.

Abstract: A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The second thermal member forms a plurality of through holes for heat dissipation. The light source is disposed on the second thermal member, and the connecting member connects the thermal module with the adapter.

Abstract: A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member which are formed by a die casting process, wherein the light source is disposed on the second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The connecting member is formed by a metal extrusion process and extends through the first thermal member to connect the second thermal member with the adapter.

Abstract: A method of forming and recognizing an identification mark for read-only memory. First, a first patterned resist layer is formed on a semiconductor substrate having an insulating region and a device region thereon by a code mask having code and identification mark patterns, and the identification mark pattern is over the insulating region. Next, ion implantation is performed to code in the device region. Thereafter, a second patterned resist layer is formed on the first patterned resist layer by a common mask to expose the entire identification mark pattern of the first patterned resist layer only. The identification mark pattern is then transferred to the insulating region by dry etching. Finally, the substrate having a clear identification mark is placed in an optical microscope for identification by an operator.

Abstract: A method of forming a MOS transistor having a p.sup.+ -polysilicon gate includes doping an amorphous silicon layer with phosphorus, thereby forming a n.sup.- amorphous silicon layer atop of a gate oxide. The n.sup.- amorphous silicon layer is then doped with boron to convert the n.sup.- amorphous silicon layer into a p.sup.+ -amorphous silicon layer. The p.sup.+ -amorphous silicon layer is then thermally treated to convert the p.sup.+ -amorphous silicon layer into a p.sup.+ -polysilicon layer. The p.sup.+ -polysilicon layer is then patterned into a gate for a MOS transistor. The phosphorus ions in the p.sup.+ -polysilicon help to fix the boron ions in the polysilicon gate, thereby reducing the diffusion of the boron ions and penetration of boron into the gate oxide.