Abstract: A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.

Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a distal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The distal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the distal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the distal clamping plate, and the connecting seat therebetween into a locked condition.

Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.

Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Abstract: A sensing device substrate includes a substrate and a sensing device. The sensing device is disposed on the substrate and includes a first electrode, a second electrode, a sensing layer, a conductive layer, and a first insulating layer. The first electrode is located on the substrate. The second electrode is overlapped with the first electrode. The sensing layer is located between the second electrode and the first electrode. The conductive layer is overlapped with the second electrode and electrically connected to the first electrode. The conductive layer has a first opening, and the first opening is overlapped with the sensing layer. The first insulating layer is located between the conductive layer and the second electrode. A display apparatus including the sensing device substrate is also provided.

Abstract: A light source assembly is provided, including a substrate; a light-emitting element disposed on the substrate; and an optical film at least partially overlapped with the substrate. A diffuser film is at least partially overlapped with the optical film, wherein a haze of the diffuser film is greater than 85%, and a thickness of the diffuser film ranges from 0.04 mm to 0.35 mm. The optical film and the diffuser film are capable of transmitting at least a part of light emitted from the light-emitting element.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.

Abstract: Embodiments disclosed herein include a method of developing a patterning stack. In an embodiment, the method comprises providing a patterning stack, where the patterning stack comprises an underlayer and a photoresist over the underlayer, and where the underlayer has a first adhesion strength with the photoresist. The method may further comprise exposing and developing the photoresist with electromagnetic radiation and a developer, where scum remains on a surface of the underlayer. In an embodiment, the method further comprises treating the underlayer so that the underlayer has a second adhesion strength with the scum, and removing the scum.

Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

Abstract: Systems and methods for presenting calendar information in electronic messages can include a data processing system receiving a request for calendar information for display in an electronic message responsive to the client device accessing the electronic message. The data processing system can identify, using information in the request, the calendar information of the sender of the electronic message and calendar information of the recipient of the electronic message. The data processing system can retrieve the calendar information of the sender of the electronic message and the calendar information of the recipient of the electronic message. The data processing system can automatically generate an image depicting the calendar information of the sender of the electronic message and the calendar information of the recipient of the electronic message, and send instructions to the client device to cause display of the image within the electronic message accessed by the client device.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: A battery-powered system includes a device and a battery. The device includes a recess for receiving the battery and an electrical contact disposed at the bottom of the recess. The device includes front and back guide elements and a spacer with a raised portion and a ramp. The battery has front and back guide elements constructed to mate with corresponding front and back guide elements of the device such that when the guide elements are mated, the battery is in a locked position. A battery electrical contact is disposed along the device-facing major surface, constructed to operatively couple with the device electrical contact. The spacer is constructed to reduce wear and damage to the electrical contacts by reducing contact with the electrical contacts while the battery is moved long the spacer.

Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a gate dielectric layer disposed over the fin structure. The semiconductor device includes an interfacial layer over a top portion of the gate dielectric layer. A bottom portion of gate dielectric layer is free of contact with the interfacial layer. The semiconductor device includes a gate structure straddling the fin structure.

Abstract: A method for promoting growth of a probiotic microorganism includes cultivating the probiotic microorganism in a growth medium containing a fermented culture of lactic acid bacterial strains that include Lactobacillus salivarius subsp. salicinius AP-32 deposited at the China Center for Type Culture Collection (CCTCC) under CCTCC M 2011127, Lactobacillus plantarum LPL28 deposited at the China General Microbiological Culture Collection Center (CGMCC) under CGMCC 17954, Lactobacillus acidophilus TYCA06 deposited at the CGMCC under CGMCC 15210, and Bifidobacterium longum subsp. infantis BLI-02 deposited at the CGMCC under CGMCC 15212.

Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.

Abstract: The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.

Abstract: A spectrum analyzing method and a gingivitis evaluating device are provided. The spectrum analyzing method includes steps as follows. A diffuse reflection signal of a gingiva is calculated, and a gingiva spectrum is generated. The gingiva spectrum and a plurality of reference gingiva spectra are respectively applied with a time-series similarity calculation, and a plurality of similarity values are generated. The plurality of reference gingiva spectra correspond to various gingival indexes (GI). A minimum similarity value of the plurality of similarity values is obtained. A GI result is output according to the minimum similarity value.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.