Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: The surface of the circuit substrate is a solder mask. The solder mask protects the electrical circuit on the circuit substrate against suffering from the environmental damage. By dividing the area of the circuit substrate into the solder mask area and the adhesive area, a bismaleimide triazine layer is formed on the surface of the circuit substrate to coarsen the adhesive area and so as to enhance the adhesion strength between the chip and the circuit substrate.

Abstract: A chip molded onto a substrate with a slot forms a molded semiconductor structure, wherein the chip covers one end of the slot and the other open. This special design leads the mold flow and enhances the semiconductor by a transverse pressure induced by the molding flow as the semiconductor is being molded. Moreover, to arrange the molded semiconductor structures especially in a cavity formed by the top portion die and bottom mold die avoids the flow spill. The special molded semiconductor structure and arrangement enhance the adhesion onto the bottom mold die to upgrade the molding quality.

Abstract: An assembly structure of thin lead-frame is provided. A lead-frame includes the plurality of leads and a layer located on the extension of the inner lead to bear a die. Then the molding compound is covered the die, the layer, and the plurality of leads but exposed the outer lead to electrically connect with different electric circuit substrates. The inner leads used as a die pad directly may reduce the size of the package. Furthermore, the assembly cost may drop dramatically and facilitate the assembly process due to the invention is totally different than prior package assembly method.

Abstract: A structure of Ball Grid Array package (BGA) is provided. The plurality of bumps are attached on a substrate when processed the surface mount technology (SMT) may get stronger support, avoid the assembly structure disintegration when bearing an external force. When user uses a semi-conductor module, the assembly structure will not be damaged by external force.