Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.