Abstract: A feed forward method for forming within a microelectronic fabrication a patterned target layer with controlled critical dimension (CD) first provides a substrate having formed thereover a blanket target layer, in turn having formed thereover a blanket anti-reflective coating (ARC) layer, in turn having formed thereover a paltered photoresist layer.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via a conductor layer refill procedure, offers a smooth top surface, flush with the top surface of the adjacent interlevel dielectric layer, for the overlying antifuse layer.

Abstract: A method for fabricating a copper, or a copper-titanium nitride-titanium, interconnect structure, using a low temperature RIE patterning procedure, has been developed. The RIE patterning procedure features the use of SiCl.sub.4 and nitrogen, as reactants, with amount of nitrogen supplied, being equal to, or greater than, the SiCl.sub.4 level. The addition of nitrogen, to the etching ambient, results in the formation of a non-cross-linked, by-product, which is easily removed during the patterning procedure, this not interfering with the creation of interconnect structure. Without the addition of nitrogen, a cross-linked, by-product, would be formed, during the low temperature RIE procedure, with the redeposited, cross-linked, by-product, interfering with the patterning of the copper interconnect structure.