Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.

Abstract: A nitride read-only memory (NROM) device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right bit. A threshold voltage difference will be obtained for the ultra cycling NROM device for the un-programmed left bit. Next, a cycling number is obtained based on the threshold voltage difference for the ultra cycling NROM device. A threshold voltage shift can be found based on the cycling number for the NROM array. Finally, an erase voltage will be calculated according to the threshold voltage shift for the NROM array. If the NROM array is programmed again, the erase voltage will be applied to un-programmed NROM devices of the NROM array to further reduce the threshold voltages.