Patents by Inventor Chi-Nung NI
Chi-Nung NI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096648Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.Type: ApplicationFiled: November 15, 2023Publication date: March 21, 2024Inventors: Sanjay Dabral, Chi Nung Ni, Long Huang, SivaChandra Jangam
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Publication number: 20240088779Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.Type: ApplicationFiled: September 21, 2023Publication date: March 14, 2024Inventors: Chi Nung Ni, Sanjay Dabral
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Publication number: 20240088032Abstract: Microelectronic modules are described. In an embodiment, a microelectronic module includes a module substrate, a chip mounted onto the module substrate, and a semiconductor-based integrated passive device between the chip and the module substrate. The semiconductor-based integrated passive device may include an upper RDL stack-up with thicker wiring layers than a lower BEOL stack-up. The semiconductor-based integrated passive device may be further solder bonded or hybrid bonded with the chip.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Inventors: Vidhya Ramachandran, Chi Nung Ni, Chueh-An Hsieh, Rekha Govindaraj, Jun Zhai, Long Huang, Rohan U. Mandrekar, Saumya K. Gandhi, Zhuo Yan, Yizhang Yang, Saurabh P. Sinha, Antonietta Oliva
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Patent number: 11862481Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.Type: GrantFiled: August 30, 2021Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Sanjay Dabral, Chi Nung Ni, Long Huang, SivaChandra Jangam
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Patent number: 11811303Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.Type: GrantFiled: September 24, 2021Date of Patent: November 7, 2023Assignee: Apple Inc.Inventors: Chi Nung Ni, Sanjay Dabral
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LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
Patent number: 11699753Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: GrantFiled: April 25, 2022Date of Patent: July 11, 2023Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Publication number: 20230098000Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Chi Nung Ni, Sanjay Dabral
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Publication number: 20220293433Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.Type: ApplicationFiled: August 30, 2021Publication date: September 15, 2022Inventors: Sanjay Dabral, Chi Nung Ni, Long Huang, SivaChandra Jangam
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LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS
Publication number: 20220254922Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
Patent number: 11316044Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: GrantFiled: June 5, 2018Date of Patent: April 26, 2022Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Publication number: 20200243659Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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Patent number: 10622452Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: GrantFiled: June 5, 2018Date of Patent: April 14, 2020Assignee: Maxim Integrated Products, Inc.Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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Publication number: 20190371902Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
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LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS
Publication number: 20180350980Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.Type: ApplicationFiled: June 5, 2018Publication date: December 6, 2018Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga -
Publication number: 20170194430Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.Type: ApplicationFiled: December 30, 2016Publication date: July 6, 2017Inventors: Bingxi Sun WOOD, Michael G. WARD, Shiyu SUN, Michael CHUDZIK, Nam Sung KIM, Hua CHUNG, Yi-Chiau HUANG, Chentsau YING, Ying ZHANG, Chi-Nung NI, Lin DONG, Dongqing YANG
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Patent number: 9673277Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.Type: GrantFiled: October 16, 2015Date of Patent: June 6, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Adam Brand, Bingxi Sun Wood, Naomi Yoshida, Lin Dong, Shiyu Sun, Chi-Nung Ni, Yihwan Kim
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Publication number: 20160111495Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.Type: ApplicationFiled: October 16, 2015Publication date: April 21, 2016Inventors: ADAM BRAND, BINGXI SUN WOOD, NAOMI YOSHIDA, LIN DONG, SHIYU SUN, CHI-NUNG NI, YIHWAN KIM
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Publication number: 20150118833Abstract: A method of depositing a contact layer material includes sputtering a target including a metal and a dopant. The contact layer material is conductive and may be used in a transistor device to connect a conductive region, such as a source region or a drain region of metal-oxide semiconductor field effect transistor, to a contact plug. The contact plug is used to connect the source/drain region formed in a semiconducting substrate to metal wiring layers formed above the gate level of a semiconductor device. The resulting contact layer may be a metal silicide including the dopant. In some embodiments, the sputtered metal may be nickel and the dopant may be phosphorous and the resulting contact layer a nickel silicide doped with phosphorous. Embodiments described, in general, can provide reduced contact resistance and thus improved performance in semiconductor devices.Type: ApplicationFiled: October 24, 2013Publication date: April 30, 2015Inventors: Jianxin LEI, Jothilingam RAMALINGAM, Chi-Nung NI