Patents by Inventor Chi-Pin Lu
Chi-Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240113061Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.Type: ApplicationFiled: December 5, 2023Publication date: April 4, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
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Patent number: 11895841Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.Type: GrantFiled: September 27, 2021Date of Patent: February 6, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Pei-Ci Jhang, Chi-Pin Lu
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Publication number: 20230403852Abstract: An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Inventors: Chi-Pin LU, Pei-Ci JHANG, Masaru NAKAMICHI, Ling-Wuu YANG, Kuang-Chao CHEN
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Publication number: 20230100464Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventors: Pei-Ci JHANG, Chi-Pin LU
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Patent number: 10714494Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.Type: GrantFiled: November 23, 2017Date of Patent: July 14, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Pei-Ci Jhang, Chi-Pin Lu
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Publication number: 20190157290Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.Type: ApplicationFiled: November 23, 2017Publication date: May 23, 2019Applicant: MACRONIX International Co., Ltd.Inventors: Pei-Ci Jhang, Chi-Pin Lu
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Patent number: 10181475Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.Type: GrantFiled: October 14, 2016Date of Patent: January 15, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Pei-Ci Jhang, Chi-Pin Lu, Jung-Yu Shieh
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Patent number: 10056395Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.Type: GrantFiled: October 11, 2016Date of Patent: August 21, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chi-Pin Lu, Pei-Ci Jhang, Fu-Hsing Chou, Chih-Hsiung Lee
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Publication number: 20180019254Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.Type: ApplicationFiled: October 14, 2016Publication date: January 18, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Pei-Ci Jhang, Chi-Pin Lu, Jung-Yu Shieh
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Publication number: 20170287921Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.Type: ApplicationFiled: October 11, 2016Publication date: October 5, 2017Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHI-PIN LU, PEI-CI JHANG, FU-HSING CHOU, CHIH-HSIUNG LEE
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Publication number: 20150171181Abstract: A method of forming a charge-trapping structure in a memory device is disclosed. The method comprises the steps of forming a gate oxide and gate electrode on a semiconductor substrate, performing undercut etching on the gate oxide layer, annealing in a nitrogen containing environment, further creating funnel-like openings on both sides of the gate oxide layer, and conformally forming the charge-trapping structure on the substrate surface.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Chi-Pin LU
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Publication number: 20140209990Abstract: A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided.Type: ApplicationFiled: January 25, 2013Publication date: July 31, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Chi-Pin Lu
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Patent number: 8581322Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.Type: GrantFiled: June 28, 2011Date of Patent: November 12, 2013Assignee: Macronix International Co., Ltd.Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
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Patent number: 8373218Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.Type: GrantFiled: October 28, 2010Date of Patent: February 12, 2013Assignee: Macronix International Co., Ltd.Inventor: Chi-Pin Lu
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Publication number: 20130001667Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
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Patent number: 8183618Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.Type: GrantFiled: December 7, 2010Date of Patent: May 22, 2012Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Chi-Pin Lu, Jung-Yu Hsieh
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Patent number: 7927660Abstract: A method of manufacturing a nano-crystalline silicon dot layer is provided. A silicon layer is formed over a substrate. The silicon layer includes crystalline silicon region and amorphous silicon region. An oxidation process is performed to oxidize the amorphous silicon region and the surfaces of the crystalline silicon region to form a silicon oxide layer containing nano-crystalline silicon dots.Type: GrantFiled: August 21, 2006Date of Patent: April 19, 2011Assignee: MACRONIX International Co., Ltd.Inventor: Chi-Pin Lu
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Publication number: 20110073937Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yen-Hao Shih, Chi-Pin Lu, Jung-Yu Hsieh
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Publication number: 20110042738Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.Type: ApplicationFiled: October 28, 2010Publication date: February 24, 2011Applicant: Macronix International Co., Ltd.Inventor: Chi-Pin LU