Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Abstract: An electrical connector for interconnecting a pair of circuit members (e.g., a circuit board and module), which, in one embodiment, includes a housing, at least one flexible circuit within the housing and a spring means attached to the flexible circuit at two spaced locations for exerting force against the flexible circuit to cause the circuit to engage respective conductive pads on the circuit members when the circuit members are moved toward each other (e.g., compressed). The shape of the spring means conforms substantially to the portion of the flexible circuit between the locations of attachment. In another embodiment, a connector for interconnecting such circuit members includes a housing adapted for being located between both members and at least one elongated, compressible contact member in the housing and including conductive end portions for engaging the circuit members.

Abstract: A multilayered circuit board assembly which includes a plurality of layered subassemblies each having electrically conducting wiring and at least one through hole therein. A first of these subassemblies possesses a greater wiring dnesity than the others while a second subassembly possesses a lesser resistance (and wiring density) than the others. In one example, several (e.g. at least four) such layered subassemblies may be included in the overall assembly such that those layers located along one side of the board may possess substantially greater wiring densities than the layers on the other side of the board while those layers on said other side will in turn possess lesser resistance (and greater current capacities). There are also described at least three methods for making the above multilayered circuit board assembly. Such a structure may be utilized in supercomputer applications.

Abstract: Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions.In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure.

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices.In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

Abstract: A semiconductor device has a heavily doped semiconductor substrate with a lightly doped epitaxial layer overlying a surface of the substrate and of the same conductivity type as the substrate. Electrically insulating barriers extend from at least the surface of the epitaxial layer into the substrate so as to electrically isolate non-common areas of each surface leakage sensitive device within the epitaxial layer from the non-common areas of adjacent surface leakage sensitive devices.

Abstract: A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern