Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell structure is provided. The flash memory cell includes a substrate, a gate structure, a source region, an erase gate, an erase gate dielectric layer, a select gate, a select gate dielectric layer and a drain region. The gate structure is set up over the substrate. The gate structure includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a spacer. The source region is formed in the substrate on one side of the gate structure. The erase gate is formed over the source region on one side of the gate structure. The erase gate dielectric layer is formed between the erase gate and the source region. The select gate is set up on another side of the gate structure. The select gate dielectric layer is formed between the select gate and the substrate. The drain region is formed in the substrate on one side of the select gate.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory device with selective gate within a substrate and method of fabricating the same. The flash memory device comprises a substrate with a floating gate disposed thereon. A wordline extends along a first direction and overlies the floating gate and the adjacent substrate thereof. A trench is disposed in the substrate adjacent to one side of the wordline. A selective gate is vertically disposed in the trench, partially covering the floating gate. A source region is disposed in the substrate adjacent to the other side of the wordline and a drain region is disposed in the substrate beneath the selective gate.

Abstract: A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.

Abstract: A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.