Patents by Inventor Chi She Chen
Chi She Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150255156Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.Type: ApplicationFiled: September 17, 2014Publication date: September 10, 2015Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20150248249Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.Type: ApplicationFiled: September 17, 2014Publication date: September 3, 2015Inventors: Mike Hossein Amidi, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20150242313Abstract: A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.Type: ApplicationFiled: September 17, 2014Publication date: August 27, 2015Inventors: Hyun Lee, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20150169238Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.Type: ApplicationFiled: November 7, 2014Publication date: June 18, 2015Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 9037809Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: July 7, 2014Date of Patent: May 19, 2015Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Patent number: 8971045Abstract: A module is electrically connectable to a computer system. The module includes an edge connector with a plurality of electrical contacts electrically connectable to the computer system, at least one layer of thermally conductive material thermally coupled to the edge connector, and first and second printed circuit boards each having a plurality of integrated circuit components that are electrically coupled to the edge connector and thermally coupled to the at least one layer of thermally conductive material. The at least one layer of thermally conductive material are disposed between the first and second printed circuit boards.Type: GrantFiled: December 30, 2012Date of Patent: March 3, 2015Assignee: NETLIST, Inc.Inventors: Robert S. Pauley, Jayesh R. Bhakta, William M. Gervasi, Chi She Chen, Jose Delvalle
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Patent number: 8904099Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.Type: GrantFiled: February 5, 2014Date of Patent: December 2, 2014Assignee: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8904098Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.Type: GrantFiled: September 24, 2012Date of Patent: December 2, 2014Assignee: Netlist, Inc.Inventors: Mike Hossein Amidi, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8880791Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.Type: GrantFiled: February 5, 2014Date of Patent: November 4, 2014Assignee: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8874831Abstract: A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.Type: GrantFiled: July 26, 2012Date of Patent: October 28, 2014Assignee: Netlist, Inc.Inventors: Hyun Lee, Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
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Patent number: 8864500Abstract: An electronic module for a computer system comprises a first circuit board having a plurality of edge connectors configured to releasably connect to electrical contacts of a computer system socket, a second circuit board having a plurality of contacts configured to connect with a plurality of electrical components, and a flexible portion having electrical conduits to provide electrical connection between the plurality of edge connectors and the plurality of contacts. The flexible portion further includes an electrically conductive layer extending across a region of the flexible portion. The electrically conductive layer is superposed with the electrical conduits and separated from electrical conduits by a dielectric layer.Type: GrantFiled: October 16, 2012Date of Patent: October 21, 2014Assignee: Netlist, Inc.Inventors: Jayesh R. Bhakta, Enchao Yu, Chi She Chen, Richard E. Flaig
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Patent number: 8782350Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: March 5, 2012Date of Patent: July 15, 2014Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Publication number: 20140156919Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.Type: ApplicationFiled: February 5, 2014Publication date: June 5, 2014Applicant: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20140156920Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.Type: ApplicationFiled: February 5, 2014Publication date: June 5, 2014Applicant: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8677060Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.Type: GrantFiled: May 29, 2013Date of Patent: March 18, 2014Assignee: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8671243Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.Type: GrantFiled: May 29, 2013Date of Patent: March 11, 2014Assignee: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20130254497Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.Type: ApplicationFiled: May 29, 2013Publication date: September 26, 2013Applicant: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Publication number: 20130254456Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.Type: ApplicationFiled: May 29, 2013Publication date: September 26, 2013Applicant: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 8516187Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.Type: GrantFiled: June 28, 2012Date of Patent: August 20, 2013Assignee: Netlist, Inc.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
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Publication number: 20130086309Abstract: A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.Type: ApplicationFiled: July 26, 2012Publication date: April 4, 2013Applicant: NETLIST, INC.Inventors: Hyun Lee, Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta