Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. A first pre-stage amplifier circuit includes a pair of first n-type transistors, and gate terminals of the first pair of the n-type transistors receive the input signal and the reference voltage signal, respectively. A second pre-stage amplifier circuit includes a pair of first p-type transistors, wherein gate terminals of the pair of the first p-type transistors receive the input signal and the reference voltage signal, respectively. The post-stage amplifier circuit outputs a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals. A memory device including the receiver circuit and an operation method thereof are also introduced.

Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. The pre-stage amplifier circuits are configured to receive an input signal and a reference voltage signal, output first pre-stage amplifying signals through a first connection node and a second connection node separately, and output second pre-stage amplifying signals through a third connection node and a fourth connection node separately. The post-stage amplifier circuit is configured to receive the first pre-stage amplifying signals and the second pre-stage amplifying signals from the pair of pre-stage amplifier circuits through the first connection node, the second connection node, the third connection node and the fourth connection node separately, and output a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals.

Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. A first pre-stage amplifier circuit includes a pair of first n-type transistors, and gate terminals of the first pair of the n-type transistors receive the input signal and the reference voltage signal, respectively. A second pre-stage amplifier circuit includes a pair of first p-type transistors, wherein gate terminals of the pair of the first p-type transistors receive the input signal and the reference voltage signal, respectively. The post-stage amplifier circuit outputs a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals. A memory device including the receiver circuit and an operation method thereof are also introduced.