Patents by Inventor Chi Wang

Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178132
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen YU, Lin-Yu HUANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240176584
    Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-acc
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Chia-Yu Chen, Andrea Fasoli, Ankur Agrawal, Kyu-hyoun Kim, Chi-Chun LIU, Mauricio J. Serrano, Monodeep Kar, Naigang Wang, Leland Chang
  • Publication number: 20240175771
    Abstract: Embodiments of the disclosure provide a method and device for providing a wire breakage warning. The method includes: obtaining a plurality of process values when a crystal ingot cutting machine uses a cutting wire to cut a crystal ingot; dividing the process values into N groups, and determining a statistical property of each of the groups; identifying outlier values in the process values based on the statistical property of each of the groups, or determining a statistical property variation corresponding to each of the groups based on the statistical property of each of the groups; and in response to determining that the outlier values in the process values meet a first warning condition, or the statistical property variation corresponding to each of the groups meets a second warning condition, providing a wire breakage warning associated with the cutting wire.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chien-Wen YU, Shang-Chi Wang, Bo-Ting Lin
  • Publication number: 20240175839
    Abstract: Defect detection method for a semi-conducting bedding layer of a power cable includes: obtaining a length parameter, a corrugation pitch parameter, radius parameters, and a thickness parameter of a power cable; obtaining a first resistance value between a shield and a corrugated sheath, and calculating a second resistance value of the shield based on the length parameter and the corrugation pitch parameter; calculating a radial resistance value of the semi-conducting bedding layer based on the first resistance value and the second resistance value; determining a contact angle of a critical point of contact between the corrugated sheath and the semi-conducting bedding layer based on the radius parameters and the thickness parameter; calculating volume resistivity of the semi-conducting bedding layer based on the radial resistance value and the contact angle; and comparing the volume resistivity with a preset evaluation parameter to obtain a defect detection result of the semi-conducting bedding layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 30, 2024
    Inventors: Shengchen Fang, Pengxian Song, Xu Li, Yang Yu, Mingzheng Zhu, Zhengzheng Meng, Fengzheng Zhou, Xiaohui Zhu, Lei Yang, Jun Zhang, Chun He, Nan Wang, Ke Xu, Qinghua Tang, Chi Zhang, Haoming Wang, Longji Li, Cheng Sun, Wei Fan
  • Patent number: 11997409
    Abstract: The embodiments of the disclosure provide a video processing method and apparatus, and terminal and storage medium. The method includes: turning on a first camera on a first side and a second camera on a second side of a terminal in response to a first preset operation, wherein the first side and the second side are opposite or have different directions; and using the first camera and the second camera for simultaneous video recording. According to the method of the disclosure, a video recording method is improved by using the cameras on two sides of the terminal for simultaneous video recording, so that more flexible choices may be provided for video presentation and editing.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 28, 2024
    Assignee: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
    Inventors: Lili Wang, Chi Fang, Dong Wang, Wei Gao, Haizhou Zhu
  • Patent number: 11993689
    Abstract: The present invention relates to a foamable composition used to prepare foamed thermoplastic polyurethane and a microwave molded body thereof. The foamable composition includes unfoamed thermoplastic polyurethane particles, a thickener or a bridging agent, and a foaming agent, wherein the unfoamed thermoplastic polyurethane particles have a viscosity of 1,000 poise to 9,000 poise measured at 170° C. according to JISK 7311 test method.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 28, 2024
    Assignee: SUNKO INK CO., LTD.
    Inventors: Ting-Kai Huang, Yi-Jung Huang, Hsin-Hung Lin, Hong-Yi Lin, Ya-Chi Wang
  • Patent number: 11995388
    Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Patent number: 11996461
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240170385
    Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Mei-Yen CHEN, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Publication number: 20240172497
    Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 23, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Weiyun HUANG, Yao HUANG, Chi YU, Xingliang XIAO, Bo SHI, Benlian WANG
  • Publication number: 20240172361
    Abstract: An electronic device is provided. The electronic device includes a substrate structure, a control unit, a first circuit structure, and an electronic unit. The substrate structure has a conductive via pattern and a dummy via pattern. The control unit is electrically connected to the conductive via pattern. The first circuit structure is electrically connected to the conductive via pattern. The electronic unit is electrically connected to the control unit through the first circuit structure. The dummy via pattern is electrically insulated from the first circuit structure.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 23, 2024
    Inventors: Cheng-Chi WANG, Kuan-Feng LEE, Jui-Jen YUEH
  • Patent number: 11989921
    Abstract: A three-dimensional data encoding method includes generating a bitstream by encoding subspaces included in a current space including three-dimensional points. In the generating of the bitstream: first information is stored in a first header which is common to the subspaces and included in the bitstream, the first information indicating first coordinates which are coordinates of the current space; and second information is stored in a second header which is provided on a subspace basis and included in the bitstream, the second information indicating a difference between second coordinates which are coordinates of a corresponding subspace among the subspaces and the first coordinates.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: May 21, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chung Dean Han, Pongsak Lasang, Chi Wang, Toshiyasu Sugio
  • Patent number: 11991433
    Abstract: Examples disclosed herein provide a computing device. As an example, the computing device includes a housing having an opening extending through the housing, to accommodate a lens of a camera. The computing device includes a shutter to selectively obscure the opening, where the shutter is slidable between a first position and a second position. While in the first position, the shutter is to obscure the opening while a microphone of the computing device is enabled and, while in the second position, the shutter is to obscure the opening and disable the microphone.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 21, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ching-Ming Wang, Hui-Jen Tseng, Yen-Chi Chen
  • Patent number: 11990545
    Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
  • Patent number: 11991436
    Abstract: A driving mechanism is provided, including a base, a movable unit, and a movable part. The movable unit is movably disposed on the base and connected to an optical element. The movable part is movably disposed on the base and forms a passage. When the movable part moves from the first position to the second position relative to the base, the movable unit can slide relative to the base from its initial position through the passage to a closed position.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 21, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Hsi Wang, Yu-Chi Kuo, Xuan-Huan Su, Yueh-Lin Lee
  • Publication number: 20240160232
    Abstract: A rotary driving device and a method for correcting a system error of the rotary driving device are provided. The rotary driving device includes a driven assembly, a driving assembly, a torque transmission member, a first torque sensor, and a second torque sensor. The driving assembly includes a fixed component and a rotating component, the rotating component is rotatably connected to the fixed component, the torque transmission member is connected to the rotating component and the driven assembly, the rotating component is configured to drive the driven assembly to rotate through the torque transmission member. The first torque sensor is connected to the fixed component and the torque transmission member, and the second torque sensor is disposed on the driven assembly.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Qingying CHEN, Guilin YANG, Chi ZHANG, Weijun WANG
  • Publication number: 20240162269
    Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate. An interconnect structure is disposed over the first substrate. The interconnect structure includes a plurality of metal features that are stacked over one another. A lowermost metal feature of the plurality of metal features is closest to the first substrate, an uppermost metal feature of the plurality of metal features is furthest from the first substrate, and intermediate metal features are disposed between the lowermost metal feature and the uppermost metal feature. A recess extends into the interconnect structure and terminates at a bond pad. A lower surface of the bond pad directly contacts an upper surface of the lowermost metal feature.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
  • Publication number: 20240162185
    Abstract: An electronic device including a circuit structure, a bonding element and an electronic unit is disclosed. The circuit structure includes a conductive pad, and the conductive pad has an accommodating recess. At least a portion of the bonding element is disposed in the accommodating recess. The electronic unit is electrically connected to the conductive pad through the bonding element. The accommodating recess has a bottom surface and an opening opposite to the bottom surface, and a width of the bottom surface is greater than a width of the opening.
    Type: Application
    Filed: December 25, 2022
    Publication date: May 16, 2024
    Applicant: InnoLux Corporation
    Inventors: Chin-Ming HUANG, Cheng-Chi WANG, Kuan-Hsueh LIN
  • Publication number: 20240164156
    Abstract: Disclosed is a display substrate including a base substrate, which includes first and second display regions, and at least one first data line. The first display region includes first and second sub-display regions located on opposite sides of the second display region along a first direction; and a third sub-display region located on at least one side of the second display region along a second direction. The first data line includes a first sub-data line located in the first sub-display region and connected with a pixel circuit of the first sub-display region, a second sub-data line located in the second sub-display region and connected with a pixel circuit of the second sub-display region, and a third sub-data line which is connected with the first and second sub-data lines, located in the third sub-display region, and connected with at least one second pixel circuit of the third sub-display region.
    Type: Application
    Filed: June 23, 2021
    Publication date: May 16, 2024
    Inventors: Jianchang CAI, Chi YU, Bo SHI, Yudiao CHENG, Zhi WANG, Benlian WANG