Abstract: A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions.