Patents by Inventor CHI-YI CHUANG
CHI-YI CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978782Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.Type: GrantFiled: June 9, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11961567Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.Type: GrantFiled: June 24, 2022Date of Patent: April 16, 2024Assignee: PUFsecurity CorporationInventors: Kai-Hsin Chuang, Chi-Yi Shao, Chun-Heng You
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Patent number: 11940737Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.Type: GrantFiled: May 7, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
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Publication number: 20240072776Abstract: An entropy source circuit, comprising: a first adjustable ring oscillator for operating under a first setting or a second setting according to a first control signal, for respectively generating a first oscillation clock signal and a second oscillation clock signal which have different frequencies under the first setting and the second setting; a first sampling circuit, for sampling the first oscillating clock signal according to the sampling frequency to generate first sampling values, or sampling the second oscillating clock signal according to the sampling frequency to generate second sampling values; a first detection circuit detecting a first distribution of the first sampling values; and a control circuit generating the first control signal to switch the first setting to the second setting when the first distribution does not meet a predetermined distribution. The entropy source circuit outputs entropy values according to the first sample value or the second sample value.Type: ApplicationFiled: July 6, 2023Publication date: February 29, 2024Applicant: PUFsecurity CorporationInventors: Chi-Yi Shao, Kai-Hsin Chuang, Meng-Yi Wu
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Publication number: 20240030189Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.Type: ApplicationFiled: August 9, 2023Publication date: January 25, 2024Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11830854Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.Type: GrantFiled: January 31, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Publication number: 20230369499Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Publication number: 20230268391Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Chi-Yi CHUANG, Cheng-Ting CHUNG, Hou-Yu CHEN, Kuan-Lun CHENG
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Patent number: 11735669Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.Type: GrantFiled: November 11, 2020Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Publication number: 20230261093Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: CHI-YI CHUANG, CHING-WEI TSAI, KUAN-LUN CHENG, CHIH-HAO WANG
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Patent number: 11652140Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.Type: GrantFiled: February 25, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yi Chuang, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11637196Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.Type: GrantFiled: March 4, 2022Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20220302280Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Yi CHUANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20220271122Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Inventors: Chi-Yi CHUANG, Cheng-Ting CHUNG, Hou-Yu CHEN, Kuan-Lun CHENG
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Publication number: 20220190144Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.Type: ApplicationFiled: March 4, 2022Publication date: June 16, 2022Inventors: CHI-YI CHUANG, CHING-WEI TSAI, KUAN-LUN CHENG, CHIH-HAO WANG
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Patent number: 11362191Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.Type: GrantFiled: May 17, 2019Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20220157786Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11271094Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a principle dimension, from a cross sectional perspective, perpendicular to a top surface of the semiconductor substrate, and a semiconductor capping layer cover the insulator fin along the principle dimension. A method for manufacturing a semiconductor structure is also disclosed in the present disclosure.Type: GrantFiled: June 19, 2019Date of Patent: March 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20220037528Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: November 11, 2020Publication date: February 3, 2022Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11239208Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.Type: GrantFiled: August 14, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng