Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

Abstract: Oral care compositions comprising (i) a stannous ion source and (ii) a chelator or an antioxidant, as well as to methods of using these compositions are disclosed herein.

Abstract: Oral care compositions comprising a stannous ion source, tetrasodium pyrophosphate and an antioxidant, as well as to methods of using these compositions are disclosed herein. In some embodiments, the antioxidant is selected from ascorbyl phosphate and ascorbate.

Abstract: A method for manufacturing an elastic fiber and the elastic fiber are provided. The method includes: providing a thermoplastic polyester elastomer; drying the thermoplastic polyester elastomer; melting the thermoplastic polyester elastomer by an extruder to form a melt; extruding the melt by a spinneret plate to form a plurality of filamentous streams; feeding the filamentous streams into a spinning channel for cooling and curing to form a plurality of monofilaments; and bundling and oiling the monofilaments by an oil wheel, after extending and guiding the monofilaments by a first godet roller and a second godet roller, and winding the monofilaments by a winder to obtain a thermoplastic polyester elastic fiber.

Abstract: Embodiments of the present invention can provide an extended NVMe driver that supports exercising virtual functions (and related physical functions) of a DUT without using a VM or hypervisor. In this way, the amount of memory and processing resources used for testing NVMe SSDs can be significantly reduced, and a large number of DUTs (e.g., up to 16 DUTs) can be tested in parallel independently. In other words, each DUT is tested in isolation, as if is the only device being tested, and there are no race conditions or competition for resources between workloads during testing.

Abstract: Automatic test equipment (ATE) configured to test devices under test (DUTs) can include a host device tester, one or more load boards, and one or more host bus adapters (HBAs). The host device tester does not support odd sector sizes and/or non-standard sector sizes. The one or more load boards can be communicatively coupled to the host device. The one or more HBAs can be communicatively coupled between respective load boards and one or more respective devices under test (DUTs). The one or more load boards can be configured to communicate with respective HBAs using one or more first communication protocol interfaces. The one or more HBAs can be configured to communicate with the respective DUTs using one or more second communication protocol interfaces. The HBAs can be configured to translate commands and data between the host device tester and the one or more DUTs that support odd sector size or non-standard sector size.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: A system and method for generating a stained image including the steps of obtaining a first image of a key sample section; and processing the first image with a multi-modal stain learning engine arranged to generate at least one stained image, wherein the at least one stained image represents the key sample section stained with at least one stain.

Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.

Abstract: A scan-type display apparatus includes an LED array and a data driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The data driver includes multiple data driving circuits, each of which includes a current driver and a detector. The current driver has an output terminal connected to the data line corresponding to the data driving circuit, and outputs one of a drive current and a clamp voltage at the output terminal of the current driver based on a pulse width control signal. The detector is connected to the current driver, and generates a detection signal that indicates whether any one of the LEDs connected to the data line corresponding to the data driving circuit is short circuited based on a detection timing signal and a feed-in voltage related to a voltage at the output terminal of the current driver.

Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.

Abstract: A method of monitoring a clock signal of a server is provided. The server includes a phase-locked loop (PLL), a baseboard management controller (BMC), and a light emitting unit. The method includes steps of: A) the server executing a time synchronization service to obtain a synchronization mode that the PLL is operating in, where the synchronization mode is one of a free-run mode, a locked mode, and a holdover mode; B) the server updating the synchronization mode to the BMC when executing the time synchronization service; and C) the BMC storing the synchronization mode and controlling the light emitting unit to display in one of a plurality of displaying manners that corresponds to the synchronization mode.

Abstract: The present disclosure relates to metrology measurement systems, and related methods. In one or more embodiments a system, includes a substrate support, and an optical arm. The optical arm includes a light source operable to project a first beam on a first light path. The optical arm also includes a first lens, a first beam splitter, a second lens, a first detector, and an aperture. The first lens is disposed on the first light path and between the substrate support and the light source. The first beam splitter is disposed on the first light path. The first beam splitter is positioned between the substrate support and the light source. The first detector is disposed on the second light path. The second lens focuses the second beam to a second beam diameter. The aperture is disposed between the second lens and the first detector.

Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.

Abstract: A back panel of a solar cell and a method for manufacturing the same are provided. The back panel includes a prepreg and a fluorine-containing polymer layer, and the fluorine-containing polymer layer is formed on the prepreg. The prepreg is formed by immersing a fiber substrate into a resin composition. Based on a total weight of the resin composition being 100 PHR (parts per hundred resin), the resin composition includes: 5 PHR to 70 PHR of a first epoxy resin, 1 PHR to 20 PHR of a hardener, and 0.01 PHR to 10 PHR of an accelerant. The first epoxy resin contains phosphorus atoms, and an amount of the phosphorus atoms in the first epoxy resin ranges from 0.1 wt % to 5 wt %.