Abstract: An asynchronous first-in first-out (AFIFO) buffer apparatus has an AFIFO buffer and a rate control circuit. The AFIFO buffer receives a data input from a first processing circuit operating under a first clock, and transmits a data output to a second processing circuit operating under a second clock, where the first clock is asynchronous to the second clock. The rate control circuit actively controls a data transfer rate of the data input regardless of a water level of the AFIFO buffer, and further adaptively applies compensation to the data transfer rate according to the water level of the AFIFO buffer.