Patents by Inventor Chia Cheng
Chia Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11992322Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.Type: GrantFiled: March 30, 2021Date of Patent: May 28, 2024Assignee: IONETWORKS INC.Inventors: Jing-Ming Guo, Ting Lin, Chia-Fen Chang, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen Wei
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Patent number: 11996405Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.Type: GrantFiled: August 27, 2021Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Jung Yu, Pin-Cheng Hsu
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Publication number: 20240171435Abstract: Techniques pertaining to optimization of distributed-tone resource unit (RU) pilot tone designs in wireless communications are described. An apparatus (e.g., station (STA)) generates a distributed-tone RU (dRU) with a respective position of each of one or more pilot tones shifted with a respective position of each of one or more other pilot tones kept unchanged. The apparatus then performs a wireless communication in a 20 MHz or 40 MHz bandwidth with the dRU.Type: ApplicationFiled: November 16, 2023Publication date: May 23, 2024Inventors: Shengquan Hu, Ching-Chia Cheng, Hung-Tao Hsieh, Jianhan Liu, Thomas Edward Pare, JR.
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Publication number: 20240170225Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
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Publication number: 20240166711Abstract: The present application provides a method for promoting the sternness and/or transdifferentiation of acinar cells, comprising the following steps: providing an acinar cell, transfecting a plasmid into the acinar cell, and culturing the transfected acinar cell, wherein the plasmid contains a genetic material for overexpression of N-acetylglucosaminyltransferase V (GnT-V).Type: ApplicationFiled: November 18, 2022Publication date: May 23, 2024Inventors: Pei-Jen Lou, Tai-Horng Young, Ching-Chia Cheng, Mei-Chun Lin, Hisn-Lin Chen
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Patent number: 11987883Abstract: A powder atomic layer deposition apparatus for blowing powders is disclosed. The powder atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit drives the vacuum chamber to rotate through the shaft sealing device. The shaft sealing device includes an outer tube and an inner tube, wherein the inner tube is arranged in an accommodating space of the outer tube. At least one air extraction line and at least one air intake line are located in the inner tube, wherein the air intake line extends from the inner tube into a reaction space within the vacuum chamber, and is used to transport the a non-reactive gas to the reaction space to blow the powders around in the reaction space.Type: GrantFiled: May 30, 2021Date of Patent: May 21, 2024Assignee: SKY TECH INC.Inventors: Jing-Cheng Lin, Jung-Hua Chang, Chia-Cheng Ku
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Patent number: 11987676Abstract: A black polyester film and a method for manufacturing the same are provided. The black polyester film includes a physically recycled polyester resin and a chemically recycled polyester resin. The physically recycled polyester resin is formed by a plurality of physically recycled polyester chips. The chemically recycled polyester resin is formed by a plurality of chemically recycled polyester chips and mixed with the physically recycled polyester resin. The plurality of chemically recycled polyester chips further include chemically recycled electrostatic pinning polyester chips. The chemically recycled electrostatic pinning polyester chips contain electrostatic pinning additives, and the electrostatic pinning additives are metal salts. Expressed in percent by weight based on a total weight of the polyester film, a content of the electrostatic pinning additives in the polyester film is between 0.005% and 0.1% by weight. The black polyester film further includes a black additive.Type: GrantFiled: March 10, 2021Date of Patent: May 21, 2024Assignee: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Wen-Cheng Yang, Chun-Cheng Yang, Chia-Yen Hsiao, Ching-Yao Yuan
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Patent number: 11990443Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.Type: GrantFiled: April 9, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
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Patent number: 11986060Abstract: A strap tip structure includes a positioning fastener member and an outer cover. The positioning fastener member includes a mainbody, at least three clip members and an external screw structure. The at least three clip members are flexibly connected to the mainbody, and each of the clip members is an arc plate and has an end portion. The external screw structure is disposed on an outer surface of the mainbody. The outer cover is detachably connected to the positioning fastener member. The outer cover includes an inner space and an inner screw structure, and the inner screw structure matches the external screw structure. When the inner screw structure of the outer cover and the external screw structure of the positioning fastener member are screwed together, the positioning fastener member is accommodated in the inner space.Type: GrantFiled: February 15, 2023Date of Patent: May 21, 2024Assignee: TAIWAN PAIHO LIMITEDInventors: Allen Cheng, Chan-Lu Chang, Chia-Ju Cheng, Yi-Jhen Su
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Publication number: 20240162809Abstract: A power supply circuit is provided. The power factor correction (PFC) circuit is used to perform a power factor correction according to a first voltage to generate an intermediate voltage. The first storage capacitor is used to store a first electrical energy related to the intermediate voltage. The boost conversion circuit is connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage. The boost conversion circuit includes a first post-stage inductor, a first post-stage diode and a first post-stage transistor. The second storage capacitor is used to store a second electrical energy related to the output voltage. The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor; the first electrical energy is completely or partially transferred as the second electrical energy.Type: ApplicationFiled: March 6, 2023Publication date: May 16, 2024Inventors: Yu-Cheng LIN, Te-Hung YU, Chia-Hui LIANG, Min-Hao HSU
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Publication number: 20240159953Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.Type: ApplicationFiled: January 26, 2024Publication date: May 16, 2024Inventors: Chia-Yin CHANG, Po-Chang HUANG, Kun-Cheng LIN
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Publication number: 20240163407Abstract: A projection system and a control method thereof are provided. The projection system includes a projector. The projector comprises a projection module and a processor. The processor is electrically coupled to the projection module. The projector confirms whether a first triggering event is detected and turns on a sleep aid mode in response to the first triggering event. The sleep aid mode corresponds to at least one control parameter. In the sleep aid mode, the projection module plays at least one multimedia file according to the at least one control parameter. The processor adjusts at least one parameter value of the at least one control parameter to adjust the at least one multimedia file correspondingly. The projector confirms whether a second triggering event is detected and the projection module stops playing the at least one multimedia file and turns off the sleep aid mode in response to the second triggering event.Type: ApplicationFiled: November 1, 2023Publication date: May 16, 2024Applicant: Optoma CorporationInventors: Yuan-Mao Tsui, Hsien-Cheng Yuan, Chia-Chien Wu, Wei-Jung Wang
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Patent number: 11981744Abstract: The present invention relates to bispecific chimeric polypeptide assembly compositions comprising bulking moieties linked to binding domains by cleavable release segments that, when cleaved are capable of concurrently binding effector T cells with targeted tumor or cancer cells and effecting cytolysis of the tumor cells or cancer cells. The invention also provides compositions and methods of making and using the cleavable chimeric polypeptide assembly compositions.Type: GrantFiled: December 19, 2022Date of Patent: May 14, 2024Assignee: AMUNIX PHARMACEUTICALS, INC.Inventors: Volker Schellenberger, Fan Yang, Desiree Thayer, Bee-Cheng Sim, Chia-Wei Wang
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Patent number: 11982936Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.Type: GrantFiled: June 30, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
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Patent number: 11983052Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.Type: GrantFiled: May 28, 2021Date of Patent: May 14, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
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Publication number: 20240152671Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.Type: ApplicationFiled: November 3, 2023Publication date: May 9, 2024Applicant: MEDIATEK INC.Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
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Publication number: 20240154014Abstract: The present disclosure provides a forksheet structure in a semiconductor device and methods of manufacturing thereof. The forksheet structure according to the present disclosure includes a dielectric wall disposed between two channel regions inside a gate structure and without extending through the sidewall spacers to the source/drain regions. In some embodiments, a cut metal gate (CMG) dielectric structure is formed in the gate structure along with the dielectric walls. A gate dielectric layer is in contact with the dielectric wall. In some embodiments, the dielectric layer surrounds semiconductor channels in the channel region. In other embodiments, the gate dielectric layer surrounds a portion of the semiconductor channels in the channel region, for example forming a ?-shape cross sectional profile around the semiconductor channel.Type: ApplicationFiled: February 7, 2023Publication date: May 9, 2024Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Chia-Hao CHANG, Chih-Hao WANG
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Publication number: 20240155491Abstract: Various solutions for low-power wake-up signal (LP-WUS) monitoring with respect to user equipment and network node in mobile communications are described. An apparatus may receive a configuration from a network node. The apparatus may comprise a main radio (MR) and a lower-power wake-up radio (LP-WUR). The apparatus may determine whether to activate or deactivate a low-power wake-up signal (LP-WUS) monitoring by the LP-WUR according to at least one pre-configured condition in the configuration. The apparatus may receive an LP-WUS from the network node via the LP-WUR in an event that the LP-WUS monitoring is activated.Type: ApplicationFiled: October 12, 2023Publication date: May 9, 2024Inventors: Chien-Chun Cheng, Wei-De Wu, Yi-Ju Liao, Yi-Chia Lo, Cheng-Hsun Li
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Publication number: 20240153887Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
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Patent number: D1027182Type: GrantFiled: August 15, 2022Date of Patent: May 14, 2024Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITEDInventors: Chun-Ming Cheng, Chih-Lin Liao, Yi-Chia Chiu, Chun-Ta Chen, Po-Lun Chen