Abstract: A first thread processor of a multi-thread processor system is operable to execute a first process, and a second thread processor of the multi-thread processor system is operable to execute a second process. A control register is operable to store priority information that is individually associated with at least one of the first thread processor and the second thread processor. The priority information identifies a prioritization of the first thread processor and/or a restriction on the second thread processor in a use of a shared hardware resource during execution of at least one of the first process and the second process.

Abstract: One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.

Abstract: One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.