Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.

Abstract: A high voltage transistor may include a stepped dielectric layer between a field plate structure and a channel region of the high voltage transistor in a substrate. The stepped dielectric layer may increase the breakdown voltage of the high voltage transistor by reducing the electric field strength near the drain region of the high voltage transistor. In particular, a portion of the stepped dielectric layer near the drain region includes a thickness that is greater relative to a thickness of another portion of the stepped dielectric layer near the gate structure. The increased thickness near the drain region provides increased electric field suppression near the drain region (which operates at high voltages). In this way, the stepped dielectric layer enables the high voltage transistor described herein to achieve higher breakdown voltages without increasing the distance between the gate structure and the drain region of a high voltage transistor.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate structure overlies a substrate between a source region and a drain region. A drift region is disposed laterally between the gate structure and the drain region. A first dielectric layer overlies the substrate. A field plate is disposed within the first dielectric layer between the gate structure and the drain region. A conductive wire overlies the first dielectric layer and contacts the field plate. At least a portion of the conductive wire directly overlies a first sidewall of the drift region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate structure overlies a substrate between a source region and a drain region. A drift region is disposed laterally between the gate structure and the drain region. A first dielectric layer overlies the substrate. A field plate is disposed within the first dielectric layer between the gate structure and the drain region. A conductive wire overlies the first dielectric layer and contacts the field plate. At least a portion of the conductive wire directly overlies a first sidewall of the drift region.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: An integrated chip includes a gate structure overlying a substrate between a source region and a drain region. A field plate is disposed within a first dielectric layer overlying the substrate. The field plate is laterally offset from the gate structure by a non-zero distance in a direction towards the drain region. An isolation structure is disposed within the substrate. The field plate directly overlies at least a portion of the isolation structure.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.