Patents by Inventor Chia-Cheng PAO
Chia-Cheng PAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936299Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: GrantFiled: September 21, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
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Publication number: 20240055295Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: October 29, 2023Publication date: February 15, 2024Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Patent number: 11842920Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: GrantFiled: June 21, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
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Patent number: 11522453Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) including a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a first source/drain region of the first switching device and a first source/drain region of the second switching device at a node. The controller is configured to alternatingly change the first and second switching devices between a first state and a second state, respectively. The first switching device is in a third state before or after the second switching device transitions between the first and second states. A subthreshold voltage is applied to a first gate of the first switching device during the third state, such that the third state is between a cutoff mode and a triode mode of the first switching device.Type: GrantFiled: April 1, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Pao, Chu Fu Chen, Chih-Hua Wang
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Publication number: 20210313218Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Patent number: 11075107Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: GrantFiled: April 1, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
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Publication number: 20210028309Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: ApplicationFiled: September 21, 2020Publication date: January 28, 2021Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO
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Patent number: 10784781Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.Type: GrantFiled: March 28, 2018Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
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Publication number: 20200235668Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) including a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a first source/drain region of the first switching device and a first source/drain region of the second switching device at a node. The controller is configured to alternatingly change the first and second switching devices between a first state and a second state, respectively. The first switching device is in a third state before or after the second switching device transitions between the first and second states. A subthreshold voltage is applied to a first gate of the first switching device during the third state, such that the third state is between a cutoff mode and a triode mode of the first switching device.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Chia-Cheng Pao, Chu Fu Chen, Chih-Hua Wang
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Patent number: 10644601Abstract: Various embodiments of the present application are directed towards a buck converter circuit including a controller circuit. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device and a source/drain terminal of the second switching device are electrically coupled. The controller is configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF. The first switching device is OFF while the second switching device is ON. The first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF.Type: GrantFiled: April 2, 2019Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Pao, Chu Fu Chen, Chih-Hua Wang
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Publication number: 20200105582Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: April 1, 2019Publication date: April 2, 2020Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Publication number: 20190393785Abstract: Various embodiments of the present application are directed towards a buck converter circuit including a controller circuit. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device and a source/drain terminal of the second switching device are electrically coupled. The controller is configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF. The first switching device is OFF while the second switching device is ON. The first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF.Type: ApplicationFiled: April 2, 2019Publication date: December 26, 2019Inventors: Chia-Cheng Pao, Chu-Fu Chen, Chih-Hua Wang
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Publication number: 20190165678Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.Type: ApplicationFiled: March 28, 2018Publication date: May 30, 2019Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO