Patents by Inventor CHIA-CHING HSU
CHIA-CHING HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996325Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.Type: GrantFiled: July 29, 2020Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
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Publication number: 20240170930Abstract: An integrated substation is provided. The integrated substation includes a cabinet and at least one airflow driver. The cabinet has a high pressure room, a low pressure room, and an exchange room located between the high pressure room and the low pressure room. The exchange room and the high pressure room are separated from each other by a first inner wall, and the exchange room and the low pressure room are separated from each other by a second inner wall.Type: ApplicationFiled: November 17, 2022Publication date: May 23, 2024Inventors: CHIA-CHING LIN, CHAO-CHUNG LIU, CHIA-TAI HSU
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Patent number: 11983680Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.Type: GrantFiled: June 12, 2021Date of Patent: May 14, 2024Assignee: CHASE SUSTAINABILITY TECHNOLOGY CO., LTD.Inventors: Yung-Fa Yang, Tsung-Tien Chen, Shao-Hsin Hsu, Bo-Wei Chen, Chia-Ching Chen, Ming-Hua Tang
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Publication number: 20240155843Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.Type: ApplicationFiled: November 28, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
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Patent number: 11956966Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.Type: GrantFiled: March 28, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventor: Chia-Ching Hsu
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Publication number: 20240057488Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.Type: ApplicationFiled: October 19, 2023Publication date: February 15, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
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Publication number: 20230161131Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a plurality of second guiding members. The first movable portion is configured to connect an optical member. The optical member is used for adjusting a direction of a light from an incident direction to an outgoing direction. The first movable portion can move relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion. The second guiding members include a first ball, a second ball, and a third ball. The first ball, the second ball, and the third ball are disposed in a plane that is perpendicular to the incident direction.Type: ApplicationFiled: January 20, 2023Publication date: May 25, 2023Inventors: Chih-Wei WENG, Chao-Chang HU, Yueh-Lin LEE, Chen-Hsien FAN, Chien-Yu KAO, Chia-Ching HSU, Sung-Mao TSAI, Sin-Jhong SONG
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Patent number: 11621271Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.Type: GrantFiled: February 16, 2021Date of Patent: April 4, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Chia-Ching Hsu
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Patent number: 11586002Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a movable portion and a fixed portion. The movable portion includes a holder for holding an optical member with an optical axis. The movable portion is movable relative to the fixed portion. The fixed portion has a housing and a base. The housing is disposed on the base, and includes a top surface and a side surface. The top surface extends in a direction that is parallel to the optical axis. The side surface extends from an edge of the top surface in a direction that is not parallel to the optical axis. The side surface has a rectangular opening.Type: GrantFiled: December 27, 2019Date of Patent: February 21, 2023Assignee: TDK TAIWAN CORP.Inventors: Chih-Wei Weng, Chao-Chang Hu, Yueh-Lin Lee, Chen-Hsien Fan, Chien-Yu Kao, Chia-Ching Hsu, Sung-Mao Tsai, Sin-Jhong Song
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Publication number: 20220310910Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.Type: ApplicationFiled: April 14, 2021Publication date: September 29, 2022Inventor: Chia-Ching Hsu
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Patent number: 11444095Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.Type: GrantFiled: April 13, 2021Date of Patent: September 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Publication number: 20220262808Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.Type: ApplicationFiled: March 28, 2022Publication date: August 18, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventor: Chia-Ching Hsu
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Publication number: 20220262806Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.Type: ApplicationFiled: February 16, 2021Publication date: August 18, 2022Inventor: Chia-Ching Hsu
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Publication number: 20220246845Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.Type: ApplicationFiled: March 9, 2021Publication date: August 4, 2022Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
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Patent number: 11387337Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.Type: GrantFiled: December 24, 2020Date of Patent: July 12, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang
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Patent number: 11127752Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.Type: GrantFiled: February 21, 2020Date of Patent: September 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang, Chun-Sung Huang
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Publication number: 20210265376Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Applicant: United Microelectronics Corp.Inventors: CHIA-CHING HSU, Wang Xiang, Shen-De Wang, Chun-Sung Huang
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Publication number: 20210233924Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Patent number: 11011535Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.Type: GrantFiled: December 22, 2019Date of Patent: May 18, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Publication number: 20210119004Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang