Patents by Inventor Chia-Ching Huang

Chia-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150162204
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Inventors: Ching-Fang Yu, Chia-Ching Huang, Ting-Hao Hsu
  • Patent number: 9046776
    Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Chia-Chen Chen, Jui-Ching Wu, Shang-Chieh Chien, Chia-Jen Chen, Chia-Ching Huang
  • Patent number: 9034665
    Abstract: Some embodiments of the present disclosure relate to a tool configuration and method for EUV patterning with a deformable reflective surface comprising a mirror or reticle. A radiation source provides EUV radiation which is reflected off the deformable reflective surface to transfer a reticle pattern to a semiconductor workpiece. A metrology tool measures a residual vector formed between a first shape of the semiconductor workpiece and a second shape of the reticle pattern. And, a topology of the deformable reflective surface is changed based upon the residual vector to minimize a total magnitude of the residual vector.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Tzu-Hsiang Chen, Chia-Hao Hsu, Chia-Chen Chen
  • Publication number: 20150104745
    Abstract: Some embodiments of the present disclosure relates to a tool configuration and method for EUV patterning with a deformable reflective surface comprising a mirror or reticle. A radiation source provides EUV radiation which is reflected off the deformable reflective surface to transfer a reticle pattern a semiconductor workpiece. A metrology tool measures a residual vector formed between a first shape of the semiconductor workpiece and a second shape of the reticle pattern. And, a topology of the deformable reflective surface is changed based upon the residual vector to minimize a total magnitude of the residual vector.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Tzu-Hsiang Chen, Chia-Hao Hsu, Chia-Chen Chen
  • Publication number: 20150099364
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Chia-Ching Huang
  • Patent number: 9003337
    Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Pei-Cheng Hsu, Chia-Ching Huang, Chih-Ming Chen, Chia-Chen Chen
  • Publication number: 20150077733
    Abstract: Some embodiments of the present disclosure relate to a method of overlay control which utilizes a deformable electrostatic chuck. The method comprises exposing a substrate to radiation which is reflected off of a reticle. The reticle is mounted to a deformable electrostatic chuck by a plurality of raised contacts, where each raised contact is configured to independently vary in height from a surface of the deformable electrostatic chuck. After exposure of the substrate to radiation which is reflected off of the reticle, a displacement between a first alignment shape formed on a first layer disposed on a surface of the substrate and a second alignment shape formed by the exposure is measured. The height of one or more of the plurality of raised contact is changed based upon the displacement to alter a surface topology of the reticle, which negates some effects of clamping topology. Other embodiments are also disclosed.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Chia-Hao Hsu, Chia-Chen Chen
  • Patent number: 8980108
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Chia-Ching Huang
  • Publication number: 20150069253
    Abstract: Some embodiments of the present disclosure related to a method to form and operate the reflective surface to compensate for aberration effects on pattern uniformity. In some embodiments, the reflective surface comprises a mirror of within reduction optics of an EUV illumination tool. In some embodiments, the reflective surface comprises a reflective reticle. An EUV reflective surface topography comprising a reflective surface is disposed on a surface of a substrate, and is manipulated by mechanical force or thermal deformation. The substrate includes a plurality of cavities, where each cavity is coupled to a deformation element configured to expand a volume of the cavity and consequently deform a portion of the reflective surface above each cavity, for local control of the reflective surface through thermal deformation of a resistive material subject to an electric current, or mechanical deformation due to pressurized gas within the cavity or a piezoelectric effect.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Chia-Hao Hsu, Tzu-Hsiang Chen, Chia-Chen Chen
  • Publication number: 20140218714
    Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao HSU, Chia-Chen CHEN, Jui-Ching WU, Shang-Chieh CHIEN, Chia-Jen CHEN, Chia-Ching HUANG
  • Publication number: 20140127836
    Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao HSU, Pei-Cheng Hsu, Chia-Ching Huang, Chih-Ming Chen, Chia-Chen Chen
  • Publication number: 20140042715
    Abstract: A chuck includes a number of gas openings positioned to provide a gas flow to a backside of a wafer secured to the chuck. The chuck also includes a number of exhaust openings positioned to exhaust the gas at a distance from a topside edge of the wafer such that adverse thermal effects on the edge are reduced to a predetermined level.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Hsu, Kipling Yeh, Chia-Ching Huang
  • Publication number: 20130286626
    Abstract: A cable management device includes a device body, a connecting member, and an extension body. The device body includes a first cable management arm and a second cable management arm. The connecting member pivotally connects a first end of the first cable management arm and a first end of the second cable management arm to attain a first cable management configuration. The connecting member is removable from the first cable management arm and the second cable management arm. In response to removal of the connecting member, two opposing ends of the extension body are respectively connected to the first end of the first cable management arm and the first end of the second cable management arm to attain a second cable management configuration. The cable management device may be included in a rack assembly.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: WEI-TIEN CHEN, YULIANTI DARMANTO, CHIA-CHING HUANG, YU-KANG LIU, HUI-WEN TSAI
  • Patent number: 8052004
    Abstract: A releasably locking lid for a beverage container is disclosed. More specifically, lid embodiments include an outer surface, an inner surface, and a lip, the lid including a center piece and an outer ring that is configured to rotate relative to the center piece to releasably lock the container within a receiving space in the lid.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: November 8, 2011
    Assignee: Misaine Trade, Inc.
    Inventors: Benjamin Cheng, Chia-Ching Huang
  • Publication number: 20100288769
    Abstract: A releasably locking lid for a beverage container is disclosed. More specifically, lid embodiments include an outer surface, an inner surface, and a lip, the lid including a center piece and an outer ring that is configured to rotate relative to the center piece to releasably lock the container within a receiving space in the lid.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 18, 2010
    Applicant: Misaine Trade, Inc.
    Inventors: Benjamin Cheng, Chia-Ching Huang
  • Publication number: 20080277257
    Abstract: A low-noise cost-effective keyboard includes keys arranged in rows and columns in a housing. Each key has a mounting member affixed to the housing, at least one button, at least one connecting member integrally connected between the mounting member and the at least one button in a manner that a top surface of the at least one button is higher in elevation than the top surface of the mounting member, and at least one stop flange protruding from a side of the button opposite to the connecting member in a manner that an end edge of the at least one stop flange is lower in elevation than a bottom surface of the button and the stop flange of one key suspends beneath one button of another key.
    Type: Application
    Filed: September 5, 2007
    Publication date: November 13, 2008
    Applicant: Universal Scientific Industrial Co., LTD.
    Inventors: Chia-Ching HUANG, Yi-Shun Huang
  • Patent number: D643040
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 9, 2011
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Stephen Sedio, Shun-Jung Chuang, Chia-Ching Huang