Patents by Inventor Chia-Ching Lee

Chia-Ching Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180145151
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Publication number: 20180097084
    Abstract: In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron containing gas and a dilute gas, and a tungsten layer is formed on the seed layer by supplying a tungsten containing gas. A flow ratio of a flow amount of the boron containing gas to a total flow amount of the boron containing gas and the dilute gas is in a range from 1/21 to 1/4.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Yu-Sheng WANG, Chi-Cheng HUNG, Chia-Ching LEE, Chung-Chiang WU
  • Patent number: 9935173
    Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Ching-Hwanq Su
  • Publication number: 20180090431
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.
    Type: Application
    Filed: November 19, 2017
    Publication date: March 29, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
  • Patent number: 9871114
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Publication number: 20170373058
    Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh Wen TSAU, Chia-Ching Lee, Chung-Chiang Wu, Da-Yuan Lee
  • Patent number: 9824969
    Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
  • Publication number: 20170330829
    Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.
    Type: Application
    Filed: May 14, 2016
    Publication date: November 16, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
  • Publication number: 20170092740
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Patent number: 9596775
    Abstract: A buffer module and a portable electronic device using the same are provided. The buffer module comprises a buffer component and a base. The buffer component comprises a protrusion. The base has a gas vent and a buffer recess corresponding to the protrusion.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 14, 2017
    Assignee: WISTRON CORPORATION
    Inventors: Chia-Ching Lee, Ta-Chun Hsiung, Min-Hao Tang, Jhih-Ming Chen
  • Publication number: 20160155811
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a first gate having top and bottom portions of different widths, the top portion of the first gate being disposed above the bottom portion of the first gate. The FinFET also includes a second gate having top and bottom portions of different widths, the top portion of the second gate being disposed above the bottom portion of the second gate. A first inter-layer dielectric layer is disposed between the first gate and the second gate in an interposed manner. The first inter-layer dielectric layer has a thickness equal to a height of the bottom portions of the first and second gates. A second inter-layer dielectric layer is patterned over the first inter-layer dielectric layer.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: HSUEH-WEN TSAU, CHIA-CHING LEE, MRUNAL A. KHADERBAD, DA-YUAN LEE
  • Patent number: 9349726
    Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Lee, Hsueh Wen Tsau, Mrunal A. Khaderbad, Da-Yuan Lee
  • Patent number: 9310671
    Abstract: A stereo imaging device is disclosed. The stereo imaging device includes a pair of holders, an imaging element, an association pillar and a pair of isometric beams. The holders are used to clamp a handheld electronic device. The imaging element includes a bottom plate having a guide slot and is movably connected to the two holders. The association pillar is fastened in the guide slot and can be moved in the guide slot along a first axis. One end of each of the two beams is pivotally connected to the association pillar, and the other ends of the beams are respectively connected to the top plates of the two holders.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 12, 2016
    Assignee: WISTRON CORPORATION
    Inventors: Jhih-Ming Chen, Chia-Ching Lee, Ta-Chun Hsiung
  • Patent number: 9304547
    Abstract: A portable electronic apparatus includes a portable electronic device and a data access device installed on the portable electronic apparatus. The data access device includes a main body, a rotary arm and a sliding arm. The rotary arm is pivoted to the main body. When the rotary arm rotates to a folding position relative to the main body, the rotary arm is contained inside the main body. When the rotary arm rotates to a fixing position relative to the main body, the rotary arm protrudes out of the main body. The sliding arm is slidably disposed on the rotary arm so as to adjust a relative position between the sliding arm and the rotary arm. The sliding arm fixes the portable electronic device with the main body as the rotary arm rotates to the fixing position relative to the main body.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 5, 2016
    Assignee: Wistron Corporation
    Inventors: Jhih-Ming Chen, Chia-Ching Lee, Shou-Yi Cheng, Ta-Chun Hsiung
  • Patent number: 9287372
    Abstract: A method is provided for forming a trench on a FinFET. In an exemplary embodiment, a first inter-layer dielectric layer is formed between a first gate and a second gate of the FinFET in an interposed manner. A second inter-layer dielectric layer is formed above the first inter-layer dielectric layer, the first gate of the FinFET, and the second gate of the FinFET. A photoresist layer is formed above the second inter-layer dielectric layer. And part of the second inter-layer dielectric layer that is not below the photoresist layer is etched.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsueh-Wen Tsau, Chia-Ching Lee, Mrunal A. Khaderbad, Da-Yuan Lee
  • Patent number: 9281553
    Abstract: A wearable device including a display unit, a conductive frame and a belt-like structure is provided. The conductive frame surrounds a display region of the display unit, and the conductive frame has a first open slot. Besides, a feeding point and a first ground point are disposed on two sides of an opening of the first open slot, and the conductive frame forms a first antenna element. The belt-like structure is respectively connected to a first edge and a second edge, which are opposite to each other, of the conductive frame.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 8, 2016
    Assignee: Wistron Corporation
    Inventors: Wen-Yi Tsai, Chia-Ching Lee
  • Publication number: 20150279837
    Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Lee, Hsueh Wen Tsau, Mrunal A. Khaderbad, Da-Yuan Lee
  • Publication number: 20150261004
    Abstract: A stereo imaging device is disclosed. The stereo imaging device includes a pair of holders, an imaging element, an association pillar and a pair of isometric beams. The holders are used to clamp a handheld electronic device. The imaging element includes a bottom plate having a guide slot and is movably connected to the two holders. The association pillar is fastened in the guide slot and can be moved in the guide slot along a first axis. One end of each of the two beams is pivotally connected to the association pillar, and the other ends of the beams are respectively connected to the top plates of the two holders.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Inventors: Jhih-Ming CHEN, Chia-Ching LEE, Ta-Chun HSIUNG
  • Publication number: 20150262827
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mrunai A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang
  • Publication number: 20150255855
    Abstract: A wearable device including a display unit, a conductive frame and a belt-like structure is provided. The conductive frame surrounds a display region of the display unit, and the conductive frame has a first open slot. Besides, a feeding point and a first ground point are disposed on two sides of an opening of the first open slot, and the conductive frame forms a first antenna element. The belt-like structure is respectively connected to a first edge and a second edge, which are opposite to each other, of the conductive frame.
    Type: Application
    Filed: June 11, 2014
    Publication date: September 10, 2015
    Inventors: Wen-Yi Tsai, Chia-Ching Lee