Patents by Inventor Chia-Fu Lin
Chia-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240184354Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, an integrated graphical processing unit (GPU), a discrete GPU, and a controller. The interface is to receive a connection to an external display device. The integrated GPU and the discrete GPU are communicatively coupled to the interface. The controller is communicatively coupled to the integrated GPU and the discrete GPU and is to deactivate the discrete GPU and activate the integrated GPU in response to detection of the external display device connected to the interface.Type: ApplicationFiled: June 29, 2021Publication date: June 6, 2024Applicant: Hewlett-Packard Development Company, L.P.Inventors: Chia-Cheng Lin, Hsin-Jen Lin, Heng-Fu Chang, Chao-Shen Chen
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Patent number: 11994809Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe positioned above the semiconductor manufacturing equipment and having a top surface and a bottom surface extending parallel to the top surface; a first branch pipe including an upstream end coupled to a source of a gas mixture and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including an upstream end and a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.Type: GrantFiled: June 20, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
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Publication number: 20240161843Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.Type: ApplicationFiled: September 20, 2023Publication date: May 16, 2024Applicant: eMemory Technology Inc.Inventors: Chia-Fu Chang, Chun-Hung Lin, Jen-Yu Peng, You-Ruei Chuang
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Patent number: 11973502Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: GrantFiled: May 1, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Publication number: 20240128291Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.Type: ApplicationFiled: June 6, 2023Publication date: April 18, 2024Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
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Publication number: 20240128233Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.Type: ApplicationFiled: June 6, 2023Publication date: April 18, 2024Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN
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Patent number: 11961890Abstract: A semiconductor device includes a semiconductor layer and a gate structure on the semiconductor layer. The gate structure includes a multi-stepped gate dielectric on the semiconductor layer and a gate electrode on the multi-stepped gate dielectric. The multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.Type: GrantFiled: August 12, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Fu Lin, Chia-Ta Hsieh, Tsung-Hao Yeh
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Patent number: 11961546Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: GrantFiled: August 2, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 8497584Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: GrantFiled: March 26, 2004Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Patent number: 7906425Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: October 13, 2006Date of Patent: March 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 7468321Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.Type: GrantFiled: May 10, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ming Ching, Chia-Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Wen-Hsiang Tseng
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Patent number: 7276454Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.Type: GrantFiled: November 2, 2002Date of Patent: October 2, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ming Ching, Chia Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Publication number: 20070028445Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: ApplicationFiled: October 13, 2006Publication date: February 8, 2007Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 7134199Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: June 13, 2002Date of Patent: November 14, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 6974659Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.Type: GrantFiled: January 16, 2002Date of Patent: December 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
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Patent number: 6918397Abstract: A flush system comprising a network of conduits, valves and screens that can be interposed between the process container and solvent re-claim tank components of a dry film photoresist (DFR) remover system, for example, that is used in the processing and packaging of integrated circuit chips. By operation of the valves in the flush system, DFR particles can be removed from the DFR remover system in order to prevent or minimize particle clogging of a particle filter in the DFR remover system. The screens in the flush system can be periodically cleaned by reverse flow of solvent or by operation of a nitrogen and DI (deionized) water purge system.Type: GrantFiled: April 22, 2002Date of Patent: July 19, 2005Assignee: Taiwan SemiconductorInventors: Ta-Min Lin, Szu-Yao Wang, Chia-Fu Lin, Kai-Ming Ching, Wen-Hsiang Tseng
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Patent number: 6805279Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: June 27, 2002Date of Patent: October 19, 2004Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Chin, Li-Chi Chen, Hao-Chih Tien
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Patent number: 6802250Abstract: A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.Type: GrantFiled: May 20, 2002Date of Patent: October 12, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen