Patents by Inventor Chia-Hao Cheng
Chia-Hao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985662Abstract: A user equipment (UE) includes one or more non-transitory computer-readable media containing computer-executable instructions embodied therein, and at least one processor coupled to the one or more non-transitory computer-readable media. The at least one processor configured to execute the computer-executable instructions to receive downlink control information (DCI) on a downlink (DL) channel of a non-terrestrial network (NTN), the DL channel reception ending in a first slot, and transmit an uplink (UL) transmission on a UL channel of the NTN in a second slot. The second slot is separate from the first slot by a timing offset, where a duration of the timing offset is dependent on a type of the UL transmission and a numerology of the UL transmission.Type: GrantFiled: September 30, 2020Date of Patent: May 14, 2024Assignee: FG Innovation Company LimitedInventors: Chien-Chun Cheng, Chia-Hao Yu, Hung-Chen Chen, Chie-Ming Chou
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Patent number: 11949920Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.Type: GrantFiled: July 24, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Ming-Hsien Lai, Min-Hao Chiu, Chia-Yun Cheng
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Patent number: 11923409Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
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Patent number: 11742301Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.Type: GrantFiled: August 19, 2019Date of Patent: August 29, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
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Patent number: 11715691Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.Type: GrantFiled: May 18, 2021Date of Patent: August 1, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
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Publication number: 20230187364Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chia-Hao Cheng, Kong Toon Ng, Rahul Agarwal, Brett P. Wilkerson
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Publication number: 20230120305Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.Type: ApplicationFiled: October 14, 2022Publication date: April 20, 2023Inventors: CHIA-HAO CHENG, RAHUL AGARWAL, CHINTAN BUCH, ARSALAN ALAM
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Patent number: 11309222Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.Type: GrantFiled: August 29, 2019Date of Patent: April 19, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Lei Fu, Milind S. Bhagavat, Chia-Hao Cheng
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Publication number: 20210313269Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.Type: ApplicationFiled: May 18, 2021Publication date: October 7, 2021Inventors: MILIND S. BHAGAVAT, RAHUL AGARWAL, CHIA-HAO CHENG
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Publication number: 20210296194Abstract: Various molded semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a routing substrate and a semiconductor chip mounted on and electrically connected to the routing substrate. The semiconductor chip has plural side surfaces. A molding layer at least partially encases the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.Type: ApplicationFiled: March 18, 2020Publication date: September 23, 2021Inventors: Priyal Shah, Rahul Agarwal, Milind S. Bhagavat, Chia-Hao Cheng
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Patent number: 11011466Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.Type: GrantFiled: March 28, 2019Date of Patent: May 18, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
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Publication number: 20210066144Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.Type: ApplicationFiled: August 29, 2019Publication date: March 4, 2021Inventors: Lei Fu, Milind S. Bhagavat, Chia-Hao Cheng
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Publication number: 20210057352Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.Type: ApplicationFiled: August 19, 2019Publication date: February 25, 2021Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
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Publication number: 20200312766Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
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Publication number: 20200294914Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.Type: ApplicationFiled: March 13, 2019Publication date: September 17, 2020Inventors: Rahul Agarwal, Chia-Hao Cheng, Milind S. Bhagavat
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Patent number: D1025864Type: GrantFiled: October 27, 2021Date of Patent: May 7, 2024Assignee: Foxtron Vehicle Technologies Co., Ltd.Inventors: Tse-Min Cheng, Lu-Han Lee, Chia-Hao Hsu