Patents by Inventor Chia-Hao Pao
Chia-Hao Pao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240341073Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Inventors: Chih-Chuan YANG, Kuo-Hsiu HSU, Chia-Hao PAO, Shih-Hao LIN
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Publication number: 20240339449Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Inventors: Chia-Hao Pao, Chih-Chuan Yang, Chih-Hsuan Chen, Shih-Hao Lin
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Publication number: 20240331765Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.Type: ApplicationFiled: June 12, 2024Publication date: October 3, 2024Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
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Publication number: 20240313119Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Patent number: 12087633Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.Type: GrantFiled: September 1, 2021Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Kuo-Hsiu Hsu, Shih-Hao Lin, Shang-Rong Li, Ping-Wei Wang
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Patent number: 12080604Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.Type: GrantFiled: July 31, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
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Patent number: 12080342Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.Type: GrantFiled: March 18, 2022Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Pao, Kian-Long Lim, Chih-Chuan Yang, Jui-Wen Chang, Chao-Yuan Chang, Feng-Ming Chang, Lien-Jung Hung, Ping-Wei Wang
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Publication number: 20240292592Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
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Patent number: 12063766Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.Type: GrantFiled: October 29, 2021Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Chia-Hao Pao, Shih-Hao Lin
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Patent number: 12063768Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.Type: GrantFiled: March 13, 2023Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Kian-Long Lim, Chia-Hao Pao, Chih-Chuan Yang, Chia-Wei Chen, Chien-Chih Lin
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Publication number: 20240260249Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.Type: ApplicationFiled: March 18, 2024Publication date: August 1, 2024Inventors: Shih-Hao Lin, Kian-Long Lim, Chih-Chuan Yang, Chia-Hao Pao, Jing-Yi Lin
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Patent number: 12040325Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.Type: GrantFiled: August 31, 2021Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Chih-Chuan Yang, Shih-Hao Lin
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Publication number: 20240234421Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.Type: ApplicationFiled: February 19, 2024Publication date: July 11, 2024Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien-Jung Hung, Shih-Hao Lin
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Patent number: 12027202Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.Type: GrantFiled: July 29, 2022Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
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Patent number: 12016169Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.Type: GrantFiled: June 16, 2022Date of Patent: June 18, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
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Patent number: 11996484Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.Type: GrantFiled: May 13, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Publication number: 20240172409Abstract: One aspect of the present disclosure pertains to a memory device. The device includes a substrate having a first region and a second region adjacent the first region. A first SRAM cell is disposed within the first region, the first SRAM cell having first active regions extending lengthwise along a first direction on the substrate. A second SRAM cell is disposed within the second region, the second SRAM cell having second active regions extending lengthwise along the first direction on the substrate. Frontside metal lines are disposed over the first and second active regions, the frontside metal lines including a first bit line and a first bit line bar within the first region. And backside metal lines are under the first and second active regions, the backside metal lines having a second bit line and a second bit line bar within the second region.Type: ApplicationFiled: March 15, 2023Publication date: May 23, 2024Inventors: Chia-Hao Pao, Kian-Long Lim
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Publication number: 20240154019Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.Type: ApplicationFiled: December 29, 2023Publication date: May 9, 2024Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Yu-Kuan Lin
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Patent number: 11980016Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.Type: GrantFiled: July 20, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
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Patent number: 11937416Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.Type: GrantFiled: May 23, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Hao Lin, Kian-Long Lim, Chih-Chuan Yang, Chia-Hao Pao, Jing-Yi Lin