Abstract: A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit and the first memory are placed in a single module.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device.

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract: The invention provides a semiconductor package structure. The semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die comprises a plurality of third pads with the first pad area and a plurality of fourth pads with the second pad area alternately arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the fourth pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device.

Abstract: An intuitive eco-driving assistance system is mounted on a vehicle and has an input module, a control module and an output module. The control module is electrically connected to the input module and the output module. The output module acquires images ahead of the vehicle and speed signals for the control module to recognize a speed limit, traffic lights and a speed and distance of any obstacle on the images. Furthermore, according to the driving limits of the road and actual vehicle speed, the output module prompts for an eco-driving instruction and the speed limit meeting the road condition visually or audibly. Accordingly, the issue of conventional vehicles being structurally complicated and costly for conserving energy, only passively prompting fuel consumption, and consuming more fuel can be solved without requiring any additional and complicated system.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

Abstract: An intuitive eco-driving assistance system is mounted on a vehicle and has an input module, a control module and an output module. The control module is electrically connected to the input module and the output module. The output module acquires images ahead of the vehicle and speed signals for the control module to recognize a speed limit, traffic lights and a speed and distance of any obstacle on the images. Furthermore, according to the driving limits of the road and actual vehicle speed, the output module prompts for an eco-driving instruction and the speed limit meeting the road condition visually or audibly. Accordingly, the issue of conventional vehicles being structurally complicated and costly for conserving energy, only passively prompting fuel consumption, and consuming more fuel can be solved without requiring any additional and complicated system.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

Abstract: The present invention discloses a sheet clamping apparatus for a reticle, a wafer, a glass substrate, a LCD panel et al. The apparatus comprises a pair of brackets, each bracket having at least one cam groove thereon for defining a movement route by two opposing sides of the cam groove, and one end of each bracket being joined with a connecting frame. One end of a clamping arm is joined with each cam groove, and the other end of the clamping arm is clamping the sheet (ex: a reticle, a wafer, a glass substrate, a LCD panel et al.). The characteristic of the sheet clamping apparatus is that: on the other end of each clamping arm is formed with a clamping head with recess, and at least a pair of rollers are disposed on the recess of clamping head for stably clamping the reticle or a semiconductor component stored in the pod.

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.