Patents by Inventor Chia Hong
Chia Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176093Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Publication number: 20240170341Abstract: Semiconductor devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing a semiconductor device includes: forming first nanostructures from a first material over a substrate; forming second nanostructures from a second material different from the first material over the substrate, wherein the first nanostructures and the second nanostructures alternate vertically above the substrate; removing the first nanostructures; after the removing the first nanostructures forming an interposer in between the second nanostructures; after the forming the interposer forming a first source/drain region over the substrate and in direct physical contact with the second nanostructures; and removing the interposer exposing surfaces of each of the second nanostructures.Type: ApplicationFiled: January 10, 2023Publication date: May 23, 2024Inventors: Yu-Ming Chen, Tsung-Lin Lee, Chia-Ho Chu, Sung-En Lin, Sen-Hong Syue
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Publication number: 20240162308Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.Type: ApplicationFiled: February 9, 2023Publication date: May 16, 2024Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
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Patent number: 11971635Abstract: A U-shaped unit and a liquid crystal element with U-shaped coplanar electrode units provided by the invention are capable of increasing a horizontal electric field intensity in a power supply state, so that when the invention is applied to be used as a liquid crystal driving element, a required horizontal electric field intensity can be achieved with a lower driving voltage to reduce a required driving power when the liquid crystal element is used as a display screen, thereby achieving an effect of power saving.Type: GrantFiled: January 16, 2023Date of Patent: April 30, 2024Assignee: TUNGHAI UNIVERSITYInventors: Chia-Yi Huang, Wei-Fan Chiang, Yi-Hong Shih
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Patent number: 11967615Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.Type: GrantFiled: December 23, 2015Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20240128341Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.Type: ApplicationFiled: December 14, 2022Publication date: April 18, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chia-Hao Chang, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang
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Publication number: 20240113128Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
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Patent number: 11950433Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jheng-Hong Jiang, Cheung Cheng, Chia-Wei Liu
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Patent number: 11946087Abstract: Provided herein are compositions and methods for co-production and recovery of two or more isoprenoids from a single recombinant cell.Type: GrantFiled: January 25, 2018Date of Patent: April 2, 2024Assignee: AMYRIS BIO PRODUCTS PORTUGAL, UNIPESSOAL, LDAInventors: Christopher J. Paddon, Victor Holmes, Chia-Hong Tsai, Yoseph Tsegaye, Phoebe Yeh
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Publication number: 20240100683Abstract: A tool box includes a base element and a cover. The base element and the cover form a box interior for receiving at least one hand-held power tool. The tool box further includes a locking tab for locking the cover to the base element. The locking tab includes an insertion tool holding device for holding at least one insertion tool.Type: ApplicationFiled: September 27, 2023Publication date: March 28, 2024Inventors: Zheyan Hong, Chia Chun Kang, Yen Tiong Tan
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Patent number: 11942563Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: June 1, 2023Date of Patent: March 26, 2024Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240086137Abstract: A near eye display system is provided. The near eye display system includes: a frame; a first near eye display mounted on the frame and configured to form a first image directly projected on a first retina of a first eye of a user; a second near eye display mounted on the frame and configured to form a second image directly projected on a second retina of a second eye of the user; and a processing unit located at the frame and configured to generate a display control signal to drive the first near eye display and the second near eye display.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
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Publication number: 20240089943Abstract: A method performed by a user equipment for a beam operation is provided. The method includes: receiving an RRC configuration for configuring a set of joint TCI states; receiving, from the BS, a MAC CE for activating a subset of joint TCI states in the set of joint TCI states, the MAC CE is used to map the subset of joint TCI states to codepoints of a TCI field in DCI; receiving the DCI indicating a joint TCI state included in the subset of joint TCI states activated by the MAC CE; determining whether the DCI includes a DL assignment; transmitting, in response to reception of the DCI, first HARQ-ACK information in a case that the DCI does not include the DL assignment; and transmitting, in response to the reception of the DCI and reception of a PDSCH, second HARQ-ACK information in a case that the DCI includes the DL assignment.Type: ApplicationFiled: January 12, 2022Publication date: March 14, 2024Applicant: FG Innovation Company LimitedInventors: CHIA-HAO YU, JIA-HONG LIOU, CHIA-HUNG LIN
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Patent number: 11927991Abstract: Embodiments of synchronized hinges for foldable displays are described. In some embodiments, a hinge may include: a first bracket coupled to a first shaft via a first arm, a second bracket coupled to a second shaft via a second arm, and a synchronization bracket coupled to the first and second shafts.Type: GrantFiled: May 12, 2021Date of Patent: March 12, 2024Assignee: Dell Products, L.P.Inventors: Christopher A. Torres, Enoch Chen, Anthony J. Sanchez, Chia-Hao Hsu, Hsu Hong Yao, Mo-Yu Zhang
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Publication number: 20240081105Abstract: A display device and method of manufacturing thereof is provided. The display device includes: a substrate; a plurality of control transistors disposed in the substrate; a multi-layer interconnect (MLI) structure on the substrate; and a luminous device layer disposed on the MLI structure. The luminous device layer includes a plurality of sub-pixels corresponding to the plurality of control transistors, respectively. The MLI structure includes a plurality of routing features and at least one light blocking feature, and the plurality of routing features electrically connect each of the plurality of control transistors to the corresponding sub-pixel, and the at least one light blocking feature is operable to block stray light generated by the luminous device layer.Type: ApplicationFiled: February 17, 2023Publication date: March 7, 2024Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
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Publication number: 20240072411Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: Pegatron CorporationInventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
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Patent number: 11914915Abstract: A near eye display system is provided. The near eye display system includes: a frame comprising a main body and two temple arms; at least one near eye sensor mounted on the main body and configured to measure user eye parameters; a first near eye display mounted on the main body and configured to form a first image projected on a first retina of a first eye; a second near eye display mounted on the main body and configured to form a second image projected on a second retina of a second eye; and a processing unit located at least at one of the two temple arms and configured to generate a display control signal based at least on the user eye parameters, wherein the display control signal drives the first near eye display and the second near eye display.Type: GrantFiled: March 21, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
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Publication number: 20240057274Abstract: An electronic device including a metal back cover, a metal frame, a first radiator and a second radiator is provided. The metal frame includes a disconnected part and two connecting parts, the two connecting parts are located at two sides of the disconnected part, separated from the disconnected part and connected to the metal back cover. A U-shaped slot is formed between the disconnected part and the metal back cover, and between the disconnected part and the two connecting parts. The first radiator is located beside the disconnected part and includes a feeding end and a first connecting end away from the feeding end, and the first connecting end is connected to the disconnected part. The second radiator is located beside the disconnected part, and includes a ground end and a second connecting end opposite to each other. The ground end is connected to the metal back cover.Type: ApplicationFiled: June 1, 2023Publication date: February 15, 2024Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chao-Hsu Wu, Hau Yuen Tan, Chih-Wei Liao, Shih-Keng Huang, Wen-Hgin Chuang, Chia-Hong Chen, Lin-Hsu Chiang, Cheng-Kuan Lin, His-Yung Chen
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Publication number: 20240038587Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.Type: ApplicationFiled: March 30, 2023Publication date: February 1, 2024Inventors: Kao-Chih Liu, Wenmin Hsu, Hsuan Jung Chiu, Yu-Ting Lin, Chia Hong Lin