Patents by Inventor Chia-Hong Jan
Chia-Hong Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967615Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.Type: GrantFiled: December 23, 2015Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20240113128Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
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Publication number: 20240038592Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: ApplicationFiled: October 11, 2023Publication date: February 1, 2024Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
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Patent number: 11881486Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: GrantFiled: February 17, 2023Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
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Patent number: 11830818Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: GrantFiled: February 1, 2022Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11824002Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: GrantFiled: June 28, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu
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Patent number: 11823954Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: GrantFiled: April 13, 2022Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
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Publication number: 20230299087Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.Type: ApplicationFiled: April 28, 2023Publication date: September 21, 2023Inventors: Curtis TSAI, Chia-Hong JAN, Jeng-Ya David YEH, Joodong PARK, Walid M. HAFEZ
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Patent number: 11764260Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.Type: GrantFiled: October 4, 2021Date of Patent: September 19, 2023Assignee: Tahoe Research, Ltd.Inventors: Walid M. Hafez, Chia-Hong Jan
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Patent number: 11737362Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.Type: GrantFiled: April 1, 2016Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11695008Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.Type: GrantFiled: April 13, 2020Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
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Publication number: 20230207569Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
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Patent number: 11688792Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.Type: GrantFiled: November 15, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
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Publication number: 20230143021Abstract: Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Applicant: Intel CorporationInventors: Daniel B. OBrien, Jeffrey S. Leib, James Y. Jeong, Chia-Hong Jan, Peng Bai, Seungdo An, Pavel S. Plekhanov, Debashish Basu
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Patent number: 11610917Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: GrantFiled: January 4, 2022Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
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Patent number: 11605632Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.Type: GrantFiled: November 17, 2021Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon, Sairam Subramanian
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Patent number: 11562999Abstract: A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.Type: GrantFiled: September 29, 2018Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Roman Olac-Vaw, Nick Lindert, Chia-Hong Jan, Walid Hafez
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Patent number: 11563000Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.Type: GrantFiled: March 25, 2020Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang, Chia-Hong Jan
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Publication number: 20220238383Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
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Publication number: 20220157729Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan