Abstract: A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.

Abstract: A programmable hardware system for machine learning (ML) includes a core and an inference engine. The core receives commands from a host. The commands are in a first instruction set architecture (ISA) format. The core divides the commands into a first set for performance-critical operations, in the first ISA format, and a second set of performance non-critical operations, in the first ISA format. The core executes the second set to perform the performance non-critical operations of the ML operations and streams the first set to inference engine. The inference engine generates a stream of the first set of commands in a second ISA format based on the first set of commands in the first ISA format. The first set of commands in the second ISA format programs components within the inference engine to execute the ML operations to infer data.

Abstract: A key structure includes a keycap, a guiding structure, a connection member and a base plate. The guiding structure is located below the keycap and includes at least one pivot shaft. The connection member includes a connection groove, and the at least one pivot shaft is connected to the connection groove. The base plate includes at least one fixing member. The connection member envelops the at least one fixing member such that the connection member is fixed to the base plate.

Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.

Abstract: A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

Abstract: A keyboard device includes a substrate, keycaps, and a frame. The substrate has a top surface and a bottom surface and includes a welding-fixing portion. The welding-fixing portion includes a through hole and an arch-shaped bridge member. The arch-shaped bridge member is connected in the through hole and divides the through hole into partition holes. The arch-shaped bridge member has an arch portion and bridge bases. The arch portion protrudes from the top surface to form a recessed portion. The frame is disposed on the top surface and includes hollow holes respectively corresponding to the keycaps. The frame includes a welding member, and the welding member includes welding posts and a welding-fixing base. The welding posts respectively pass through spaces between the edge portion of the through hole and the arch-shaped bridge member. The welding-fixing base is received and fixed in the through hole and the recessed portion.

Abstract: A processing unit of an inference engine for machine learning (ML) includes a first data load steamer, a second data load streamer, an operator component, and a store streamer. The first data load streamer streams a first data stream from an on-chip memory (OCM) to the operator component. The second data load streamer streams a second data stream from the OCM to the operator component. The operator component performs a matrix operation on the first data stream and the second data stream. The store streamer receives a data output stream from the operator component and to store the data output stream in a buffer.

Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation/function. The inline post processing unit is further configured to accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables, and stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.

Abstract: A programmable hardware architecture for machine learning (ML) is proposed, which includes at least a host, a memory, a core, a data streaming engine, a instruction-streaming engine, and an interference engine. The core interprets a plurality of ML commands for a ML operation and/or data received from the host and coordinate activities of the engines based on the data in the received ML commands. The instruction-streaming engine translates the ML commands received from the core and provide a set of programming instructions to the data streaming engine and the inference engines based on the translated parameters. The data steaming engine sends one or more data streams to the inference engine in response to the received programming instructions. The inference engine then processes the data streams received from the data stream engine according to the programming instructions received from the instruction-streaming engine.

Abstract: An array-based inference engine includes a plurality of processing tiles arranged in a two-dimensional array of a plurality of rows and a plurality of columns. Each processing tile comprises at least one or more of an on-chip memory (OCM) configured to load and maintain data from the input data stream for local access by components in the processing tile and further configured to maintain and output result of the ML operation performed by the processing tile as an output data stream. The array includes a first processing unit (POD) configured to perform a dense and/or regular computation task of the ML operation on the data in the OCM. The array also includes a second processing unit/element (PE) configured to perform a sparse and/or irregular computation task of the ML operation on the data in the OCM and/or from the POD.

Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.

Abstract: A keyboard includes a base plate, a membrane circuit board, a backlight module, and a plurality of keyswitch assemblies. The base plate has a plurality of through holes. The membrane circuit board is disposed on the base plate. The backlight module is disposed at a side of the base plate away from the membrane circuit board and configured to emit light toward the base plate. The keyswitch assemblies are disposed on the membrane circuit board. Each of the keyswitch assemblies includes a position-returning member located over one of the through holes. An orthogonal projection of the position-returning member projected on the base plate overlaps a part of said one of the through holes.

Abstract: A processing unit of an inference engine for machine learning (ML) includes a first, a second, and a third register, and a matrix multiplication block. The first register receives a first stream of data associated with a first matrix data that is read only once. The second register receives a second stream of data associated with a second matrix data that is read only once. The matrix multiplication block performs a multiplication operation based on data from the first register and the second register resulting in an output matrix. A row associated with the first matrix is maintained while rows associated with the second matrix is fed to the matrix multiplication block to perform a multiplication operation. The process is repeated for each row of the first matrix. The third register receives the output matrix from the matrix multiplication block and stores the output matrix.

Abstract: The keyboard device includes a substrate, a key, a first elastic member, and a second elastic member. The substrate includes a top surface having an assembly area. The assembly area has a pivoting base including a standing portion and an extension portion extending from the standing portion. The key is liftably disposed over the assembly area. A pivoting hook is extending from the bottom of the key toward the assembly area, and one end of the pivoting hook includes a pivoting portion. The first elastic member and the second elastic member are disposed on the assembly area and elastically abutted against the bottom of the key, so that the pivoting portion is abutted against and pivoted to the extension portion, and a liftable distance is maintained between the extension portion and the bottom of the key.

Abstract: A keyboard device includes a substrate, a connection hook, a keycap, and a connecting member. The substrate has a top surface including an assembly area. The connection hook is disposed on the assembly area and includes a fixed seat fixed on the substrate, a standing portion, and a reinforcement block. The standing portion is extending from the fixed seat and extending in a direction away from the fixed seat. A hook portion is laterally extending from a top end of the standing portion, the hook portion has a bottom edge. The reinforcement block is connected to the standing portion and the bottom edge. The keycap is disposed on the assembly area. The connecting member is connected between the keycap and the assembly area. The connecting member includes a shaft slidably pivoted at the bottom edge. An inner side of the shaft includes an avoidance groove corresponding to the reinforcement block.

Abstract: A keyboard device includes a substrate, keycaps, and a frame. The substrate has a top surface and a bottom surface and includes a welding-fixing portion. The welding-fixing portion includes a through hole and an arch-shaped bridge member. The arch-shaped bridge member is connected in the through hole and divides the through hole into partition holes. The arch-shaped bridge member has an arch portion and bridge bases. The arch portion protrudes from the top surface to form a recessed portion. The frame is disposed on the top surface and includes hollow holes respectively corresponding to the keycaps. The frame includes a welding member, and the welding member includes welding posts and a welding-fixing base. The welding posts respectively pass through spaces between the edge portion of the through hole and the arch-shaped bridge member. The welding-fixing base is received and fixed in the through hole and the recessed portion.

Abstract: A keyboard device includes a substrate, a membrane circuit board, a flexible printed circuit board, a first fixing board, and a second fixing board. The substrate includes a top surface, a bottom surface, and a side edge. The substrate further includes an offset protrusion protruding from the top surface and forms a recessed area on the bottom surface. The membrane circuit board is disposed on the top surface. The membrane circuit board includes an outlet area correspondingly disposed on the offset protrusion. The flexible printed circuit board is disposed on the bottom surface. The flexible printed circuit board includes a fixed portion, a folded portion, and an electrical connection end. The fixed portion is received in the recessed area. The first fixing board is correspondingly disposed on the offset protrusion. The second fixing board is correspondingly received in the recessed area and assembled with the first fixing board.

Abstract: The present disclosure discloses a keyboard including a base plate, membrane circuit board, a plurality of keys and a frame. The base plate includes a plurality of assembly areas and a first opening. The first opening is disposed between some said assembly areas. The membrane circuit board is disposed above the base plate. The membrane circuit board includes a second opening corresponding in position to the first opening, respectively. The frame is disposed above the base plate, and the membrane circuit board is disposed between the base plate and the frame. The frame blocks the first and second openings. The frame includes receiving portions corresponding in position to the assembly areas. The keys pass through the receiving portions and are fixed to the assembly areas of the base plate, respectively. Gaps between the frame and keys, the first and second openings jointly form an air current channel.

Abstract: A keyboard includes a substrate, a limit connecting member, a keycap, and a liftable connecting member. The assembly area of the substrate includes a long fixation hole having two short sides, a first long side, and a second long side. A portion of the bottom surface of the substrate is further recessed to form a long bottom groove, and two ends of the long bottom groove are near to the two short sides. The limit connecting member is disposed on the assembly area and includes a fixed seat in the long fixation hole and a standing portion extending from the fixed seat. The fixed seat includes a lower wing plate correspondingly fixed in the long bottom groove. The keycap is disposed on the assembly area. The liftable connecting member is connected between the keycap and the assembly area and includes a shaft disposed on the limit connecting member.

Abstract: An array-based inference engine includes a plurality of processing tiles arranged in a two-dimensional array of a plurality of rows and a plurality of columns. Each processing tile comprises at least one or more of an on-chip memory (OCM) configured to load and maintain data from the input data stream for local access by components in the processing tile and further configured to maintain and output result of the ML operation performed by the processing tile as an output data stream. The array includes a first processing unit (POD) configured to perform a dense and/or regular computation task of the ML operation on the data in the OCM. The array also includes a second processing unit/element (PE) configured to perform a sparse and/or irregular computation task of the ML operation on the data in the OCM and/or from the POD.