Patents by Inventor Chia-Kuang Lee

Chia-Kuang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10854555
    Abstract: A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 1, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Chiang Lin, Chia-Kuang Lee, Shih-Ci Yen