Patents by Inventor Chia Li

Chia Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11989062
    Abstract: A display device including: a flexible display panel including two fixing portions and a bendable portion between the fixing portions; a supporting component including two supporting portions arranged on surfaces of the fixing portions to support the flexible display panel along a X direction; at least one rotating shaft located between the supporting portions and arranged to correspond to the bendable portion; at least one sliding component including a first sliding member and a second sliding member that are slidably connected in the X direction, the first sliding member is connected to one supporting portion, the second sliding member is rotatably connected to the rotating shaft; at least one driving component including a first magnetic member and a second magnetic member, a magnetic force between the first and second magnetic members drive the first sliding member to move away from the rotating shaft.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: May 21, 2024
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Chia-Huan Chang, Linlin Li
  • Publication number: 20240162372
    Abstract: A light-emitting device includes a semiconductor epitaxial structure that has a first surface and a second surface opposite to the first surface, and that includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed in such order in a direction from the first surface to the second surface. The active layer includes well layers and barrier layers that are alternately stacked. The active layer has an upper surface that is adjacent to the second semiconductor layer, and a lower surface that is opposite to the upper surface. The first semiconductor layer is doped with an n-type dopant, which has a first concentration of 5E17/cm3 at a first point in the first semiconductor layer. The first point of the first semiconductor layer and the lower surface of the active layer have a first distance therebetween. The first distance ranges from 150 nm to 500 nm.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: Weihuan LI, Jinghua CHEN, Huan-Shao KUO, Yu-Ren PENG, Dongpo CHEN, Chia-Hung CHANG
  • Patent number: 11983052
    Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 14, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
  • Publication number: 20240155491
    Abstract: Various solutions for low-power wake-up signal (LP-WUS) monitoring with respect to user equipment and network node in mobile communications are described. An apparatus may receive a configuration from a network node. The apparatus may comprise a main radio (MR) and a lower-power wake-up radio (LP-WUR). The apparatus may determine whether to activate or deactivate a low-power wake-up signal (LP-WUS) monitoring by the LP-WUR according to at least one pre-configured condition in the configuration. The apparatus may receive an LP-WUS from the network node via the LP-WUR in an event that the LP-WUS monitoring is activated.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 9, 2024
    Inventors: Chien-Chun Cheng, Wei-De Wu, Yi-Ju Liao, Yi-Chia Lo, Cheng-Hsun Li
  • Publication number: 20240147867
    Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Applicant: Intel Corporation
    Inventors: Punyashloka Debashis, Dominique A. Adams, Hai Li, Chia-Ching Lin, Dmitri Evgenievich Nikonov, Kaan Oguz, John J. Plombon, Ian Alexander Young
  • Patent number: 11972974
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Publication number: 20240136471
    Abstract: A light-emitting device includes an epitaxial structure having a first surface and a second surface that is opposite to the first surface. The epitaxial structure includes, along a first direction from the first surface to the surface, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer including a capping layer. The capping layer includes at least Ni number of sub-layers arranged in the first direction, where N1?2. Each of the sub-layers of the capping layer contains a material represented by Aly1Ga1-y1InP, where 0<y1?1. The capping layer has an Al content which increases and then remains constant along the first direction. A light-emitting apparatus includes the light-emitting device is also provided.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Weihuan LI, JInghua CHEN, Yu-Ren PENG, Huan-Shao KUO, Chia-Hung CHANG
  • Publication number: 20240128233
    Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN
  • Publication number: 20240130040
    Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.
    Type: Application
    Filed: September 7, 2023
    Publication date: April 18, 2024
    Applicant: Innolux Corporation
    Inventors: Ker-Yih Kao, Kuang-Ming Fan, Chia-Lin Yang, Jui-Jen Yueh, Ju-Li Wang
  • Publication number: 20240128291
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
  • Patent number: 11955554
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Patent number: 11950016
    Abstract: The present invention provides a control method of a receiver. The control method includes the steps of: when the receiver enters a sleep/standby mode, continually detecting an auxiliary signal from an auxiliary channel to generate a detection result; and if the detection result indicates that the auxiliary signal has a preamble or a specific pattern, generating a wake-up control signal to wake up the receiver before successfully receiving the auxiliary signal having a wake-up command.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chih-Hung Pan, Chia-Chi Liu, Shun-Fang Liu, Meng-Kun Li, Chao-An Chen
  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240097444
    Abstract: Embodiments of the present invention provide a hybrid system and method for distributed virtual power plants integrated intelligent net zero. In this method, a cyber physical agent (CPA) is utilized to collect a carbon emission information and an energy management information, and then an artificial intelligence (AI) optimization model of an intelligent central dispatch platform is utilized to obtain a power dispatch manner of the distributed virtual power plants based on the carbon emission information and the energy management information, such that the power dispatch manner of the distributed virtual power plants meets the requirements of enterprise economic benefits and net zero carbon emissions at the same time.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 21, 2024
    Inventors: Ting-Chia OU, Hao TIENG, Fan-Tien CHENG, Tsung-Han TSAI, Yu-Yong LI
  • Publication number: 20240095755
    Abstract: A hybrid method for green intelligent manufacturing (GiM) combines the carbon reduction and the energy saving into the intelligent manufacturing based Industry 4.1 cloud platform. GiM assists companies to achieve the goal of net zero transition and help them advance to Industry 4.2 as soon as possible by simultaneously taking carbon footprint and energy issues into account. GiM collects large volumes of essential data (including carbon footprint) via cyber physical agents (CPAs), and sends them to two critical services of carbon management and intelligent energy management system (iEMS) deployed on the cloud platform. The two critical services optimize the energy dispatch schedule by strictly following the requirements of energy saving, carbon reduction, and net zero. Then, the state of zero defects of intelligent manufacturing achieved in Industry 4.1 can be upgraded to net zero of GiM in Industry 4.2.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 21, 2024
    Inventors: Hao TIENG, Fan-Tien CHENG, Ting-Chia OU, Tsung-Han TSAI, Yu-Yong LI
  • Patent number: 11935639
    Abstract: An augmented reality interactive rehabilitation system includes an augmented reality eyewear device, a holding seat, a haptic module and sensing modules. The holding seat has a first recess and a second recess smaller in cross section than the first recess. The haptic module is removably placeable into the holding seat, and has a first end to be received in the first recess and a second end to be received in the second recess. The sensing modules are informationally connected to the augmented reality eyewear device and disposed in the holding seat to detect whether the haptic module is placed in a correct position.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: March 19, 2024
    Inventors: Ping-Chia Li, Jyh-Bin Suen, Wan-Chien Yang
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11929327
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240077688
    Abstract: An optical assembly (100) for use in a wearable device is provided, the assembly (100) comprising: a prism (104), a photonic integrated chip, PIC (108), a substrate layer (106), and a lid (102); wherein the PIC (108) is mounted onto the substrate layer (106); the prism (104) comprising: (i) a first input/output surface (112) optically coupled to the PIC (108), and (ii) a second input/output surface (114) optically coupled to the lid (102), the second input/output surface (114) orientated perpendicularly to the first input/output surface (112), and wherein the prism (104) provides an optical path and reflects a percentage of light from the first input/output surface (112) to the second input/output surface (114). Methods of manufacturing such an optical assembly are also provided.
    Type: Application
    Filed: January 6, 2022
    Publication date: March 7, 2024
    Inventors: Chia-Te Chou, William Vis, Alexander Gondarenko, Shuhe Li, David McCann, Haydn Frederick Jones, Alexander Fast