Patents by Inventor Chia-Liang Tsai

Chia-Liang Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120437
    Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Chen TSAI, Jia-Liang TU, Chi-Ling LEE
  • Publication number: 20240094464
    Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 21, 2024
    Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, De-Yang Chiou, Yung-Lung Lin, Chia-Shiung Tsai
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Patent number: 11925033
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
  • Patent number: 8962769
    Abstract: The present invention relates to novel polyimidothioethers-inorganic nanoparticle hybrid material, which exhibit good surface planarity, thermal dimensional stability, tunable refractive index, and high optical transparency upon forming into films. The present invention also relates to polyimidothioethers which is an intermediate for preparing the present hybrid material, and their preparation.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 24, 2015
    Assignee: National Taiwan University
    Inventors: Guey-Sheng Liou, Chia-Liang Tsai, Hung-Ju Yen, Wen-Chang Chen, Wen-Yen Chiu, Yang-Yen Yu
  • Publication number: 20130296501
    Abstract: The present invention relates to novel polyimidothioethers-inorganic nanoparticle hybrid material, which exhibit good surface planarity, thermal dimensional stability, tunable refractive index, and high optical transparency upon forming into films. The present invention also relates to polyimidothioethers which is an intermediate for preparing the present hybrid material, and their preparation.
    Type: Application
    Filed: June 27, 2012
    Publication date: November 7, 2013
    Inventors: Guey-Sheng LIOU, Chia-Liang Tsai, Hung-Ju Yen, Wen-Chang Chen, Wen-Yen Chu, Yang-Yen Yu