Patents by Inventor Chia-Lin Hsu
Chia-Lin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990339Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.Type: GrantFiled: August 2, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
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Publication number: 20240155843Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.Type: ApplicationFiled: November 28, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
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Patent number: 11966241Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.Type: GrantFiled: February 11, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
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Publication number: 20240120735Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
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Publication number: 20240113099Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.Type: ApplicationFiled: April 28, 2023Publication date: April 4, 2024Inventors: Chia-Lin HSU, Yu-Ti SU
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Patent number: 11942467Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.Type: GrantFiled: June 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
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Patent number: 11855452Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.Type: GrantFiled: December 9, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin Hsu
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Patent number: 11848554Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.Type: GrantFiled: October 26, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Lin Hsu, Ming-Fu Tsai, Yu-Ti Su, Kuo-Ji Chen
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Patent number: 11726465Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.Type: GrantFiled: August 8, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Lee-Chun Chen, Yi-Chien Yang, Chia-Lin Hsu
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Patent number: 11699618Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.Type: GrantFiled: August 12, 2020Date of Patent: July 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Yi Lee, Chia-Lin Hsu
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Publication number: 20230105593Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin HSU
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Patent number: 11557895Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.Type: GrantFiled: July 29, 2021Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin Hsu
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Publication number: 20220401548Abstract: Provided is a vaccine composition including a recombinant DNA vaccine against a pathogen. The recombinant DNA vaccine includes an expression cassette operably linked to a promoter, and the expression cassette encodes a non-structural protein of a Sindbis virus and an antigenic protein of the pathogen. Also provided is a method of producing a protective immune response against a pathogen in a subject in need thereof by administering the vaccine composition to the subject.Type: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Applicant: National Yang Ming Chiao Tung UniversityInventors: Chia-Lin HSU, Lih-Hwa Hwang, Jian Wen Heng
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Publication number: 20220375801Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.Type: ApplicationFiled: August 8, 2022Publication date: November 24, 2022Inventors: LEE-CHUN CHEN, YI-CHIEN YANG, CHIA-LIN HSU
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Publication number: 20220367259Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Yi LEE, Chia-Lin HSU
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Patent number: 11493909Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.Type: GrantFiled: April 16, 2021Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Lee-Chun Chen, Yi-Chien Yang, Chia-Lin Hsu
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Publication number: 20220352709Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.Type: ApplicationFiled: July 29, 2021Publication date: November 3, 2022Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin HSU
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Publication number: 20220344929Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.Type: ApplicationFiled: October 26, 2021Publication date: October 27, 2022Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
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Publication number: 20220334570Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: LEE-CHUN CHEN, YI-CHIEN YANG, CHIA-LIN HSU
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Publication number: 20220176372Abstract: A cartridge for a bioreactor adapted for accommodating a plurality of objects includes a cartridge main body defining a plurality of spaced-apart accommodating slots for respectively accommodating the objects therein. The cartridge main body includes a retaining portion extending into at least one of the accommodating slots, and adapted to retain a corresponding one of the objects in a corresponding one of the accommodating slots. The retaining portion is pushable to move resiliently in the corresponding one of the accommodating slots.Type: ApplicationFiled: March 31, 2021Publication date: June 9, 2022Applicant: GENEREACH BIOTECHNOLOGY CORPORATIONInventors: Wen-Shan YANG, Ching-Ko LIN, Chia-Lin HSU, Fu-Chun LI, Pin-Hsing CHOU, Yun-Lung TSAI, Pei-Yu LEE, Hsiao-Fen CHANG