Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.

Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.

Abstract: The present disclosure provides an electronic device including a first electronic unit, a second electronic unit, a circuit layer, a protection layer, and a flexible member. The first electronic unit is electrically connected to the second electronic unit through the circuit layer. The protection layer is disposed corresponding to the first electronic unit and the second electronic unit, and the protection layer has an opening. At least a portion of the flexible member is disposed in the opening. The protection layer has a first Young's modulus, the flexible member has a second Young's modulus, and the first Young's modulus is greater than the second Young's modulus.

Abstract: An electronic device includes an electronic unit, a circuit layer and a bonding pad. The electronic unit includes a chip, an insulating layer and a first conductor layer. The insulating layer is disposed on the chip, the insulating layer includes a first opening, and the first conductor layer is disposed in the first opening. The circuit layer is disposed corresponding to the electronic unit, and the circuit layer includes a second opening and a second conductor layer disposed in the second opening. The bonding pad is in contact with the second conductor layer, and the bonding pad is electrically connected to electronic unit. The first conductor layer has a first height, the second conductor layer has a second height, and a ratio of the first height to the second height is greater than or equal to 0.1 and less than or equal to 0.9.

Abstract: An electronic device is provided. The electronic device includes an electronic unit, a protective layer, and a circuit layer. The electronic unit includes a chip unit, a first insulating layer, and a second insulating layer. The first insulating layer is disposed on the chip unit, and the second insulating layer is disposed on the first insulating layer. The second insulating layer has a first side. The first side overlaps the chip unit along the normal direction of the electronic unit. The protective layer surrounds the electronic unit, and the circuit layer electrically connects the electronic unit.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: An electronic device and a manufacturing method thereof are disclosed. The electronic device includes a connector, an electronic component, and a heat sink. The connector has at least one conductive structure and at least one first heat dissipation structure. The at least one conductive structure and the at least one first heat dissipation structure are physically separated and electrically insulated from each other. The electronic component is electrically connected to the at least one conductive structure. The heat sink is connected to the at least one first heat dissipation structure. The heat sink and the electronic component are disposed on opposite sides of the connector.

Abstract: A method for manufacturing a multi-layered structure on a supporting entity is provided. The method includes forming a first layer and a first test mark on the supporting entity, wherein the first test mark has a first predetermined length. The first projected length of the first test mark is measured in a top view. The first warpage degree of the first test mark is calculated according to the first predetermined length and the first projected length.

Abstract: An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

Abstract: The present disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a connecting element. The connecting element includes a first conductive line segment, a second conductive line segment, and a first connecting line segment. The first conductive line segment is electrically connected to the second conductive line segment through the first connecting line segment. In a vertical projection direction, the first connecting line segment has a first height, the first conductive line segment has a second height, and the first height is different from the second height.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

Abstract: Examples provided herein describe a female connector in a computing device that includes a plurality of sensors for determining if a male connector has established a proper connection with the female connector. To do so, in one example, each of the sensors is coupled to an actuator that protrudes into an aperture defined by an inner surface of the female connector. As the male connector is inserted into this aperture, the actuators are pressed down which activates the sensors. Furthermore, the actuators are arranged such that a first actuator is deeper within the aperture than a second actuator. Thus, if the male connector pressed down the first actuator but not the second, a computing device can determine that only a partially connection was made. By using at least two actuators arranged at different depths in the aperture, the computing device is able to detect a proper or improper connection.

Abstract: A method for executing a plurality of child kernels invoked on a device side is provided. The child kernels are invoked in response to a parent kernel launched from a host side. The method includes the following steps: linking the child kernels to enqueue a plurality of threads of the child kernels; regrouping the threads of the child kernels to generate a plurality of thread blocks each having N threads, wherein N is a positive integer greater than one; merging the thread blocks to generate a consolidated kernel; and executing the consolidated kernel on the device side to execute a kernel function of the child kernels.

Abstract: A thread block managing method, applied to an electronic apparatus comprising a memory and a cache, comprising: (a) transforming memory addresses for the memory to cache addresses of the cache; (b) mapping a memory access range for a thread block to the cache addresses to generate a block access range; (c) calculating block locality between the thread blocks according to the block access range; and (d) allocating the thread blocks to a plurality of multi-processors depending on the block locality.

Abstract: A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.