Patents by Inventor Chia-Ling Kao

Chia-Ling Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140024220
    Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.
    Type: Application
    Filed: December 21, 2012
    Publication date: January 23, 2014
    Inventors: Chih-Yang Chang, Sean S. Kang, Chia-Ling Kao, Nikolaos Bekiaris
  • Patent number: 7981812
    Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: July 19, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kang-Lie Chiang, Chia-Ling Kao
  • Publication number: 20090293907
    Abstract: Methods for cleaning a substrate are provided. In one embodiment, the method includes depositing a polymer on a substrate. A cleaning gas is provided to clean a frontside, a bevel edge, and a backside of the substrate. The cleaning gas may include various reactive chemicals such as H2 and N2 in one embodiment. In another embodiment, the cleaning gas may include H2 and H2O. Plasma is initiated from the cleaning gas and used to remove polymer that formed on a bevel edge, backside, or frontside of the substrate during semiconductor processing.
    Type: Application
    Filed: October 6, 2008
    Publication date: December 3, 2009
    Inventors: Nancy Fung, Siyi Li, Ying Rui, Walter R. Merry, Anchel Sheyner, Kathryn Keswick, Shing-Li Sung, Mang-Mang Ling, Chia-Ling Kao, Wei-Te Wu, Kang-Lie Chiang
  • Publication number: 20090035944
    Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 5, 2009
    Inventors: Kang-Lie Chiang, Chia-Ling Kao