Patents by Inventor Chia-Lun Hang
Chia-Lun Hang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7801308Abstract: A device and method for protecting HDCP cryptographic keys are presented herein. The device and method include receiving a set of HDCP cryptographic keys, encoding the set of HDCP cryptographic keys such that the resultant encoded cryptographic data is enabled to be represented in rows and columns, and storing the set of keys in a storage device of an HDCP appliance in the rows and columns, wherein at least one of the rows does not include a complete cryptographic key and at least one of the columns does not include a complete cryptographic key. The method can use block interleaving or convolution interleaving encoding.Type: GrantFiled: July 17, 2006Date of Patent: September 21, 2010Assignee: Integrated Device Technology, Inc.Inventor: Chia Lun Hang
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Patent number: 7512763Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.Type: GrantFiled: October 19, 2006Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventor: Chia-Lun Hang
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Patent number: 7206943Abstract: Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.Type: GrantFiled: March 29, 2004Date of Patent: April 17, 2007Assignee: Genesis Microchip Inc.Inventors: Osamu Kobayashi, Ali Noorbakhsh, Chia-Lun Hang, Jih-Hsien Soong, Tzoyao Chan
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Publication number: 20070038803Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.Type: ApplicationFiled: October 19, 2006Publication date: February 15, 2007Inventor: Chia-Lun Hang
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Patent number: 7139893Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.Type: GrantFiled: October 30, 2001Date of Patent: November 21, 2006Assignee: Micron Technology, Inc.Inventor: Chia-Lun Hang
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Patent number: 6845450Abstract: Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.Type: GrantFiled: August 31, 2000Date of Patent: January 18, 2005Assignee: Genesis Microchip Inc.Inventors: Osamu Kobayashi, Ali Noorbakhsh, Chia-Lun Hang, Jih-Hsien Soong, Tzoyao Chan
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Publication number: 20040186991Abstract: Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.Type: ApplicationFiled: March 29, 2004Publication date: September 23, 2004Applicant: Genesis Microchip CorporationInventors: Osamu Kobayashi, Ali Noorbakhsh, Chia-Lun Hang, Jih-Hsien Soong, Tzoyao Chan
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Publication number: 20030084234Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.Type: ApplicationFiled: October 30, 2001Publication date: May 1, 2003Inventor: Chia-Lun Hang
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Patent number: 5974494Abstract: A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers.Type: GrantFiled: February 28, 1997Date of Patent: October 26, 1999Assignee: Samsung Electronics Co., Ltd.Inventor: Chia-Lun Hang
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Patent number: 5923665Abstract: A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.Type: GrantFiled: September 19, 1997Date of Patent: July 13, 1999Assignee: Cirrus Logic, Inc.Inventors: Yuanyuan Sun, Chih-Ta Sung, Jih-Hsien Soong, Richard Chang, Tzoyao Chan, Chia-Lun Hang
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Patent number: 5859635Abstract: A method and apparatus for automatically synchronizing the polarity of video signals generated by a graphics controller card to a display monitor is described. The present invention includes hardware circuitry comprising a storage unit, a detection unit, a selection unit that store, detect, and select input video signals, particularly a vertical and a horizontal synchronization signals, with the same or different polarity that are received from the graphics controller to a display monitor. The present invention synchronizes the polarity of input vertical and horizontal synchronization signals from the graphics controller prior to transmitting the sync signals to the display monitor. The detect and selection circuits of the present invention enable polarity of input sync signals to be synchronized without the use of software as practiced in the prior art.Type: GrantFiled: September 3, 1997Date of Patent: January 12, 1999Assignee: Cirrus Logic, Inc.Inventors: Chia-Lun Hang, Jih-Hsien Soong
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Patent number: 5838380Abstract: A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.Type: GrantFiled: December 23, 1994Date of Patent: November 17, 1998Assignee: Cirrus Logic, Inc.Inventors: Yuanyuan Sun, Chih-Ta Sung, Jih-Hsien Soong, Richard Chang, Tzoyao Chan, Chia-Lun Hang
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Patent number: 5649127Abstract: A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers.Type: GrantFiled: May 4, 1994Date of Patent: July 15, 1997Assignee: Samsung Semiconductor, Inc.Inventor: Chia-Lun Hang
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Patent number: 5487049Abstract: A page in, burst-out FIFO buffer that stores only words in a single page and transfers the words to a DRAM utilizing a page mode transfer to increase data throughput and decrease latency offloading DRAM bandwidth.Type: GrantFiled: November 23, 1994Date of Patent: January 23, 1996Assignee: Samsung Semiconductor, Inc.Inventor: Chia-Lun Hang