Patents by Inventor Chia-Lung Chang

Chia-Lung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990889
    Abstract: A bulk acoustic wave resonator and a formation method thereof are provided. The method for forming the bulk acoustic wave resonator includes forming a sacrificial structure on a substrate. A seed layer is formed on the sacrificial structure. A bottom electrode is formed on the seed layer. A piezoelectric layer is formed on the bottom electrode. A top electrode is formed on the piezoelectric layer. The sacrificial structure is removed to form a cavity. The seed layer is etched through the cavity.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 21, 2024
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Kuo-Lung Weng, Chia-Ta Chang, Tzu-Sheng Hsieh, Chun-Ju Wei
  • Publication number: 20240164007
    Abstract: The disclosure provides an electronic assembly, a method for manufacturing electronic assembly, and a composite thermally conductive sheet. The electronic assembly includes a circuit board, a heat source, an anti-overflow element, a thermally conductive block and a thermally conductive sheet. The heat source is disposed on and electrically connected to the circuit board. The anti-overflow element is disposed on a side of the heat source located farthest away from the circuit board and has an opening. The thermally conductive block is disposed on a side of the anti-overflow element located farthest away from the heat source. The thermally conductive sheet is made of a phase change material. The thermally conductive sheet is located in the opening of the anti-overflow element to be surrounded by the anti-overflow element. Opposite sides of the thermally conductive sheet are in thermal contact with the heat source and the thermally conductive block, respectively.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 16, 2024
    Applicants: MICRO-STAR INT'L CO.,LTD., MSI COMPUTER (SHENZHEN) CO.,LTD.
    Inventors: Cheng-Lung CHEN, Chia-Ming CHANG
  • Publication number: 20240155185
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
  • Publication number: 20240134631
    Abstract: An information handling system includes a memory and a processor. The memory stores a current basic input/output system (BIOS) firmware image. During a regular boot mode of the information handling, the processor creates a first set of tables associated with the current BIOS firmware image, stores the first tables to the memory, and receives a BIOS firmware update image. During a BIOS update boot mode of the information handling system, the processor creates a second plurality of tables associated with the BIOS firmware update image, and compares the first and second tables. In response to a difference being determined between the first and second tables, the processor aborts the BIOS update boot mode and generate an error log.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Shekar Babu Suryanarayana, Karunakar Poosapalli, Hung V. Ho, James L. Walker, Tsung-Lin Chuang, Chia-Hao Chang, Te-Lung Lin
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: 10903328
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10811272
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Patent number: 10790289
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Patent number: 10770464
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
  • Publication number: 20200227269
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 16, 2020
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10643883
    Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 5, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Hsuan-Tung Chu, Yi-Wei Chen, Wei-Hsin Liu, Yu-Cheng Tung, Chia-Lung Chang
  • Publication number: 20200075397
    Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 5, 2020
    Inventors: Po-Chun Chen, Hsuan-Tung Chu, Yi-Wei Chen, Wei-Hsin Liu, Yu-Cheng Tung, Chia-Lung Chang
  • Publication number: 20200020693
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Patent number: 10535664
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Publication number: 20190363093
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Application
    Filed: June 19, 2018
    Publication date: November 28, 2019
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Patent number: 10475900
    Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Tsun-Min Cheng, Chih-Chieh Tsai, Jui-Min Lee, Yi-Wei Chen, Chia-Lung Chang, Wei-Hsin Liu
  • Patent number: 10468417
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 5, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Publication number: 20190287976
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Application
    Filed: April 23, 2018
    Publication date: September 19, 2019
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Publication number: 20190280095
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Application
    Filed: April 3, 2018
    Publication date: September 12, 2019
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai