Patents by Inventor Chia-Ming Hsieh

Chia-Ming Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Publication number: 20240097027
    Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming PAN, Chia-Ta HSIEH, Po-Wei LIU, Yun-Chi WU
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 10499501
    Abstract: A cover window is provided and includes a substrate and a coating layer. The substrate has a thickness of 60 to 120 ?m. The substrate has a Re of 6000 to 12000. The coating layer is coated on the substrate. The cover window has a first direction and a second direction. The first direction is a machine direction of the cover window. The second direction is perpendicular to the first direction. A tensile stress of 50 to 130 MPa is exerted in the first direction. A tensile stress of 140 to 300 MPa is exerted in the second direction. Since the substrate has a Re of 6000 to 12000, a penetrating ray of an incident ray is uniformly distributed on a visible region of the cover window, so as to reduce the phase difference between reflected rays, reduce rainbow patterns, and enhance visibility under a polarizer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 3, 2019
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Jen Chen, Nan-Tsun Kuo, Chia-Ming Hsieh, Tzu-Hsiang Lin
  • Publication number: 20180143740
    Abstract: A cover window is provided and includes a substrate and a coating layer. The substrate has a thickness of 60 to 120 ?m. The substrate has a Re of 6000 to 12000. The coating layer is coated on the substrate. The cover window has a first direction and a second direction. The first direction is a machine direction of the cover window. The second direction is perpendicular to the first direction. A tensile stress of 50 to 130 MPa is exerted in the first direction. A tensile stress of 140 to 300 MPa is exerted in the second direction. Since the substrate has a Re of 6000 to 12000, a penetrating ray of an incident ray is uniformly distributed on a visible region of the cover window, so as to reduce the phase difference between reflected rays, reduce rainbow patterns, and enhance visibility under a polarizer.
    Type: Application
    Filed: May 18, 2017
    Publication date: May 24, 2018
    Inventors: Chun-Jen CHEN, Nan-Tsun Kuo, Chia-Ming Hsieh, Tzu-Hsiang Lin
  • Publication number: 20170027060
    Abstract: A method for forming electrode patterns on a substrate is disclosed. A layer of conductive materials is formed on the substrate, and a portion of the conductive materials is annealed by an exposing manner. The layer of conductive materials after being exposed includes an annealed first portion and an unannealed second portion. One of the annealed first portion or the unannealed second portion is removed from the substrate to form electrode patterns on the substrate.
    Type: Application
    Filed: December 11, 2015
    Publication date: January 26, 2017
    Inventors: TE-JEN TSENG, CHIA-MING HSIEH, TZU-HSIANG LIN
  • Publication number: 20150261252
    Abstract: A thin film touch panel structure includes a sensor film, a cover glass having a top surface and a bottom surface, and an optical adhesive layer between the sensor film and the cover glass. The sensor film is adhered to the bottom surface of the cover glass through the optical adhesive layer. The optical adhesive layer or any layer in the sensor film provides a sharp cutoff of UV light with a wavelength below 400 nm.
    Type: Application
    Filed: June 1, 2015
    Publication date: September 17, 2015
    Inventors: Nan-Tsun Kuo, Chia-Ming Hsieh, Tzu-Hsiang Lin, Yen-Heng Huang
  • Patent number: 8610999
    Abstract: A display element, a display apparatus and a fabricating method of a display element are provided. The display apparatus includes a first substrate, a second substrate and a display medium layer. The display medium layer is disposed between a first electrode layer of the first substrate and a second electrode layer of the second substrate. The display medium layer has a plurality of display elements. Each display element includes a colorized capsule, a fluid and a plurality of particles. The fluid and the particles are disposed in the colorized capsule, and the particles are charged. The fabricating method of a display element is coloring a capsule of a display element with dye to form a colorized capsule.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 17, 2013
    Assignee: Chimei InnoLux Corporation
    Inventors: Chia-Ming Hsieh, Jui-Jen Yueh, Sheng-Chang Chen, Sheng-Tien Cho, Wei-Lun Liao
  • Publication number: 20130295274
    Abstract: A method for manufacturing a color film substrate including the following steps is provided. A substrate is provided. A first conductive black matrix extending along a first direction is formed on the substrate. A color film layer is formed on the substrate, and the normal projections of the color film layer and of the first conductive black matrix on the substrate are not overlapping. A plurality of insulating spacers is formed on the first conductive black matrix, and the height of the insulating spacers is greater than the thickness of the color film layer. A second conductive black matrix extending along a second direction and covering the insulating spacers is formed on the substrate. A passivation layer is formed for covering the first conductive black matrix, the color film layer, the insulating spacers and the second conductive black matrix. A transparent conductive layer is formed on the passivation layer.
    Type: Application
    Filed: June 14, 2012
    Publication date: November 7, 2013
    Applicant: SHUN ON ELECTRONIC CO., LTD.
    Inventors: Lien-Hsin Lee, Jun-Yong Zhang, Chia-Ming Hsieh, Ren-Hung Wang
  • Publication number: 20130265272
    Abstract: A touch display panel including a substrate, a touch unit, a display unit, a circuit film and a flexible circuit board is provided. The substrate has a display region and a peripheral region surrounding the display region. The touch unit is disposed on the substrate and located in the display region. The display unit is disposed on the touch unit and located in the display region of the substrate. The circuit film is disposed on the substrate and located in the peripheral region, wherein the circuit film is electrically connected to the touch unit, and the circuit film has a plurality of key patterns. The flexible circuit board is electrically connected to the touch unit and the circuit film.
    Type: Application
    Filed: June 8, 2012
    Publication date: October 10, 2013
    Applicant: SHUN ON ELECTRONIC CO., LTD.
    Inventors: Chao-Sung Li, Lien-Hsin Lee, Chia-Ming Hsieh
  • Publication number: 20120274626
    Abstract: A depth map generating device. A first depth information extractor extracts a first depth information from a main two dimensional (2D) image according to a first algorithm and generates a first depth map corresponding to the main 2D image. A second depth information extractor extracts a second depth information from a sub 2D image according to a second algorithm and generates a second depth map corresponding to the sub 2D image. A mixer mixes the first depth map and the second depth map according to adjustable weighting factors to generate a mixed depth map. The mixed depth map is utilized for converting the main 2D image to a set of three dimensional (3D) images.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Applicant: HIMAX MEDIA SOLUTIONS, INC.
    Inventor: Chia-Ming Hsieh
  • Publication number: 20120008189
    Abstract: A display element, a display apparatus and a fabricating method of a display element are provided. The display apparatus includes a first substrate, a second substrate and a display medium layer. The display medium layer is disposed between a first electrode layer of the first substrate and a second electrode layer of the second substrate. The display medium layer has a plurality of display elements. Each display element includes a colorized capsule, a fluid and a plurality of particles. The fluid and the particles are disposed in the colorized capsule, and the particles are charged. The fabricating method of a display element is coloring a capsule of a display element with dye to form a colorized capsule.
    Type: Application
    Filed: May 26, 2011
    Publication date: January 12, 2012
    Applicant: CHIMEI INNOLUX CORPORATION
    Inventors: CHIA-MING HSIEH, JUI-JEN YUEH, SHENG-CHANG CHEN, SHENG-TIEN CHO, WEI-LUN LIAO
  • Patent number: 6947295
    Abstract: A ball grid array package includes a chip having a substrate with a bottom surface, a plurality of solder bumps projecting outwardly from the bottom surface of the substrate, and an electromagnetic shield including a housing that defines an inner space which receives the chip and the solder bumps therein, and a bottom opening for access into the inner space. The solder bumps project outwardly of the inner space through the bottom opening in the housing.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: September 20, 2005
    Assignee: Benq Corporation
    Inventor: Chia-Ming Hsieh
  • Publication number: 20050076729
    Abstract: An eccentric wheel unit includes a driven shaft; a rotary arm having a first end perpendicularly fixed to the driven shaft; an eccentric hammer member defining a mass center which is spaced apart from the driven shaft about a predetermined distance; and a distance adjuster mounted within the eccentric hammer member for varying the predetermined distance. The distance adjuster has a first side connected to a second end of the rotary arm. When the driven shaft rotates, the rotary arm rotates and moves the distance adjuster to cause the mass center to move away from the driven shaft.
    Type: Application
    Filed: December 6, 2004
    Publication date: April 14, 2005
    Inventor: Chia-Ming Hsieh
  • Publication number: 20050002520
    Abstract: A housing fabricating mechanism is used for fabricating a first housing and a second housing of a wireless communication devices, and the housing fabricating mechanism comprises a first fabricating surface of the first housing and a second fabricating surface of the second housing. Where the first fabricating surface of the first housing comprises a first hook and an inserted ditch, the second fabricating surface of the second housing comprises a second hook, an inserting end and a stopper for combining with the first housing fabricating surface. The second hook is located in the opposite position of the first hook and has an opening on the second housing for accommodating and wedging the first hook when the first housing and the second housing are fabricated together. The stopper is used for plugging the opening when the first housing and the second housing are fabricated together so as to prevent the first hook from detaching from the second hook after the two are wedged together.
    Type: Application
    Filed: June 18, 2004
    Publication date: January 6, 2005
    Inventors: Chin-Kai Sun, Chia-Ming Hsieh
  • Publication number: 20040160749
    Abstract: A mechanism for connecting a horizontal upper circuit board to a horizontal lower circuit board includes two insulating bodies fixed respectively on two opposite side portions of the lower circuit board, and two flexible retaining hooks fixed respectively on and projecting respectively and upwardly from the insulating bodies. Each of the insulating bodies has an inner side surface that is formed with a row of pin holes, each of which has a resilient conductive pin mounted therein. The upper circuit board is retained between the retaining hooks, and is clamped between abutment faces of the retaining hooks and upper contact portions of the conductive pins.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Applicant: BENQ CORPORATION
    Inventors: Chin-Kai Sun, Chia-Ming Hsieh
  • Publication number: 20040150977
    Abstract: A ball grid array package includes a chip having a substrate with a bottom surface, a plurality of solder bumps projecting outwardly from the bottom surface of the substrate, and an electromagnetic shield including a housing that defines an inner space which receives the chip and the solder bumps therein, and a bottom opening for access into the inner space. The solder bumps project outwardly of the inner space through the bottom opening in the housing.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 5, 2004
    Inventor: Chia-Ming Hsieh