Patents by Inventor Chia Ping Lu

Chia Ping Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 11973040
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Patent number: 11963348
    Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
  • Patent number: 11940659
    Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 10296115
    Abstract: A touch display apparatus having a fan-out side is provided. The touch display apparatus includes a first substrate, a second substrate, a touch sensing element and a display element. The first and the second substrate have a first surface and a second inner surface, respectively. The second substrate is disposed opposite to the first substrate. The second inner surface faces the first inner surface. The second substrate has a convex part and a concave part on the fan-out side. The second inner surface has a second outer lead bonding region in the convex part. The first outer lead bonding region of the first substrate is unshielded by the second substrate through the concave part. The second outer lead bonding region of the second substrate is unshielded by the first substrate. The touch sensing element and the display element are packaged in between the first and the second substrates.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 21, 2019
    Assignee: AU OPTRONICS CORP.
    Inventors: Chun-Chi Lai, Chee-Wai Lau, Feng-Sheng Lin, Yi-Ru Su, Chi-Chun Liao, Rong-Ann Lin, Chia-Ping Lu, An-Hsiung Hsieh, Pei-Yu Chen, Tsang Hong Wang, Tzu-Chi Tseng, Chung-Hao Cheng, Hsu Sheng Hsu
  • Publication number: 20160306478
    Abstract: A touch display apparatus having a fan-out side is provided. The touch display apparatus includes a first substrate, a second substrate, a touch sensing element and a display element. The first and the second substrate have a first surface and a second inner surface, respectively. The second substrate is disposed opposite to the first substrate. The second inner surface faces the first inner surface. The second substrate has a convex part and a concave part on the fan-out side. The second inner surface has a second outer lead bonding region in the convex part. The first outer lead bonding region of the first substrate is unshielded by the second substrate through the concave part. The second outer lead bonding region of the second substrate is unshielded by the first substrate. The touch sensing element and the display element are packaged in between the first and the second substrates.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 20, 2016
    Inventors: CHUN-CHI LAI, CHEE-WAI LAU, FENG-SHENG LIN, YI-RU SU, CHI-CHUN LIAO, RONG-ANN LIN, CHIA-PING LU, AN-HSIUNG HSIEH, PEI-YU CHEN, TSANG HONG WANG, TZU-CHI TSENG, CHUNG-HAO CHENG, HSU SHENG HSU
  • Publication number: 20040212987
    Abstract: An illuminating design housing which may be transparent or semi-transparent is provided wherein a lamp bulb is located at a lower portion of the housing and emits projected light through the housing to provide visual effects and permits location of objects contained within the housing.
    Type: Application
    Filed: January 21, 2004
    Publication date: October 28, 2004
    Inventor: Chia-Ping Lu
  • Publication number: 20040128879
    Abstract: This invention relates to a display apparatus which comprises the transparent container has at least one open end and a space. The jelly layer and the max layer are filled in the transparent container. The upper of the transparent container is the max layer which can seal up the jelly layer so that the liquid in the jelly layer won't permeate or evaporate. The jelly layer is used to display the floating decoration. The max layer has the candlewick thereon to display the decoration by using the projected candlelight and lamplights to enhance the practical and ornamental functions. A lighting device can be placed under the display apparatus to display another scene trough the various layers of light.
    Type: Application
    Filed: December 19, 2003
    Publication date: July 8, 2004
    Inventor: Chia Ping Lu