Patents by Inventor Chia-Sheng Lu

Chia-Sheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010456
    Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: June 11, 2024
    Assignee: MEDIATEK INC.
    Inventors: Yao-Sheng Wang, Pei-Kuei Tsung, Chia-Ni Lu, Yu-Sheng Lin, Chien-Yu Huang, Chih-Wen Goo, Cheng-Lung Jen
  • Publication number: 20240172273
    Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Cheng-Yi Chang, Kun-Sheng Huang, Yi-Hsuan Chung, Chung-Kai Hsu, Chia-Hsiang Chang, Kai Ying Lu
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Patent number: 11963348
    Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
  • Patent number: 11942380
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 8527674
    Abstract: Embodiments related to switching of data packets have been described.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: September 3, 2013
    Assignee: Lantiq Deutschland GmbH
    Inventors: Stefan Eder, Friedrich Geissler, Chia-Sheng Lu
  • Patent number: 7920592
    Abstract: A method of bandwidth control and a corresponding bandwidth control device are disclosed, in which a plurality of queues are provided, bandwidth is assigned to each of the queues on the basis of a strict priority scheme, and additional bandwidth is assigned to the queues on the basis of a fair queuing scheme.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 5, 2011
    Assignee: Lantiq Deutschland GmbH
    Inventors: Chia Sheng Lu, Sam Chu
  • Publication number: 20090190588
    Abstract: Embodiments related to switching of data packets have been described.
    Type: Application
    Filed: March 8, 2007
    Publication date: July 30, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stefan Eder, Friedrich Geissler, Chia Sheng Lu
  • Publication number: 20080151920
    Abstract: A method of bandwidth control and a corresponding bandwidth control device are disclosed, in which a plurality of queues are provided, bandwidth is assigned to each of the queues on the basis of a strict priority scheme, and additional bandwidth is assigned to the queues on the basis of a fair queuing scheme.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 26, 2008
    Applicant: Infineon Technologies AG
    Inventors: Chia Sheng Lu, Sam Chu
  • Patent number: 6684335
    Abstract: A communication network implements a “resistance cell architecture.” Each cell in the architecture comprises communication equipment such as a cell communication device coupled to one or more computers or terminals. Each cell is only permitted to communicate directly with certain predetermined other cells in the architecture. If a cell has a communication to be transmitted to a cell to which it does not directly communicate, the communication will be sent from one cell to another until the communication reaches the intended recipient. A security breach in the network can quickly, easily and effectively be isolated using the resistance cell architecture. For example, once a security is detected, the cell through which the security intrusion is detected can be deactivated or destroyed thereby preventing communications from the infected cell or branch of the resistance cell architecture to reach other parts of the network.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: January 27, 2004
    Inventors: Edwin A. Epstein, III, Souk Souvannavong, Chia-Sheng Lu
  • Patent number: 6396400
    Abstract: A security system includes a data storage device in which data or other information to be protected is stored. The data storage device, control logic, and other components are contained in a sealed first inner housing. The data storage device stores the data to be protected. The first inner housing is contained within a sealed second inner housing by a plurality of support structures which create an interstitial volume surrounding the first inner enclosure. Both inner housings are contained within an outer housing. A vacuum is created in the interstitial volume between the two inner housings. Both inner housings are sealed thereby precluding air from entering the interstitial volume and defeating the vacuum. One or more pressure sensors monitor the vacuum pressure. If an attempt is made to access the first inner housing, by drilling through the second inner housing or otherwise defeating the second inner housing's seal, the pressure of the interstitial volume will change.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: May 28, 2002
    Inventors: Edwin A. Epstein, III, Souk Souvannavong, Chia-Sheng Lu