Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

Abstract: A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: A semiconductor device, including a first metal strip extending in a first direction on a first plane; a second metal strip extending in the first direction on a second plane over the first metal strip; a third metal strip immediate adjacent to the second metal strip and extending in the first direction on the second plane; and a fourth metal strip immediate adjacent to the third metal strip and extending in the first direction on the second plane; wherein the first metal strip and the second metal strip are directed to a first voltage source; wherein a distance between the second metal strip and the third metal strip is greater than a distance between the third metal strip and the fourth metal strip.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Abstract: A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer.

Abstract: The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.