Abstract: An electronic circuit includes a first transistor coupled between a first node and a supply voltage and controlled by a first node, a second transistor coupled between a second node and the supply voltage and controlled by the first node, a third transistor coupled between a third node and the supply voltage and controlled by a fourth node, a fourth transistor coupled between the fourth node and the supply voltage and controlled by the fourth node, a fifth transistor coupled between the first node and the fifth node and controlled by a reference voltage, a sixth transistor coupled between the second node and a ground and controlled by the third node, a seventh transistor coupled between the fourth node and the ground and controlled by the second node, a first resistor coupled the fourth node to the ground, and a second resistor coupled to the fifth node.

Abstract: A current sensing amplifier circuit includes: an amplifier configured to generate an output voltage correlated with a current to-be-sensed according to a first input voltage at a first input end and a second input voltage at a second input end in a normal operation mode; and a current source circuit configured to generate a trimming current according to the first input voltage and a reference voltage in a trimming mode and to provide the trimming current to trim an offset referred to input (RTI) voltage generated by the current sensing amplifier circuit in the normal operation mode. The current source circuit is coupled between: a first resistor and a non-inverting input end, a second resistor and the output voltage, a third resistor and the non-inverting input end, or a fourth resistor and an inverting input end.

Abstract: A reference signal generator having high order temperature compensation includes: first and second transistors generating a proportional to absolute temperature (PTAT) signal and at least one complementary to absolute temperature (CTAT) signal according to at least one bandgap related to the first and second transistors; a feedback network coupled to the first and second transistors; an amplifier circuit configured to linearly superimpose the PTAT signal and the CTAT signals via the feedback network, to generate a reference signal; a second order adjustment circuit including a third transistor controlled by a bias voltage, to generate an adjustment current for adjusting the reference signal; and a third order adjustment circuit configured to adjust the bias voltage according to a temperature under test, for adjusting the adjustment current, to adjust the reference signal, such that a variation of the reference signal is smaller than a predetermined variation range within a temperature range.

Abstract: A reference signal generator having high order temperature compensation includes: first and second transistors generating a proportional to absolute temperature (PTAT) signal and at least one complementary to absolute temperature (CTAT) signal according to at least one bandgap related to the first and second transistors; a feedback network coupled to the first and second transistors; an amplifier circuit configured to linearly superimpose the PTAT signal and the CTAT signals via the feedback network, to generate a reference signal; a second order adjustment circuit including a third transistor controlled by a bias voltage, to generate an adjustment current for adjusting the reference signal; and a third order adjustment circuit configured to adjust the bias voltage according to a temperature under test, for adjusting the adjustment current, to adjust the reference signal, such that a variation of the reference signal is smaller than a predetermined variation range within a temperature range.

Abstract: An electronic circuit includes a first transistor coupled between a first node and a supply voltage and controlled by a first node, a second transistor coupled between a second node and the supply voltage and controlled by the first node, a third transistor coupled between a third node and the supply voltage and controlled by a fourth node, a fourth transistor coupled between the fourth node and the supply voltage and controlled by the fourth node, a fifth transistor coupled between the first node and the fifth node and controlled by a reference voltage, a sixth transistor coupled between the second node and a ground and controlled by the third node, a seventh transistor coupled between the fourth node and the ground and controlled by the second node, a first resistor coupled the fourth node to the ground, and a second resistor coupled to the fifth node.

Abstract: A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.

Abstract: A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.