Patents by Inventor Chia-Wen Hsu

Chia-Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 11996484
    Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Patent number: 11990339
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240114688
    Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11916151
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
  • Publication number: 20230083055
    Abstract: A driving circuit for driving a light source and a projection device are provided. The driving circuit includes a power converter, a detection circuit, and a control circuit. The power converter provides a driving power to the light source. The detection circuit provides a feedback signal according to a current value of the light source. The control circuit receives an operation command and the feedback signal. The control circuit determines whether the driving circuit enters a light-load state according to at least one of the operation command and the feedback signal. When the driving circuit is determined to enter the light-load state, the control circuit controls the power converter to decrease a current value of the driving power and controls the power converter to increase a switching frequency of the driving power. The driving circuit and the projection device may prevent the light source from flickering under the light-load state.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 16, 2023
    Applicant: Coretronic Corporation
    Inventors: Chia-Wen Hsu, Chen-Wang Chen, Tung-Min Lee
  • Publication number: 20210123233
    Abstract: A clean energy power supply system includes a container, a thermal insulation wall, a power-generation device, a power-conversion device, and a power-distribution device. The container has an internal space and a rear door. The thermal insulation wall is located in the internal space and adjacent to the rear door. The power-generation device is disposed in an accommodating space of the container and configured to generate a clean power. The power-conversion device is disposed in the accommodating space and configured to convert the clean power into a converted power. The power-distribution device is disposed in the accommodating space and configured to output the converted power to an external load or an external power grid. The thermal insulation wall is configured to block external airflow flowing through the rear door so as to maintain the temperature of the accommodating space.
    Type: Application
    Filed: November 27, 2019
    Publication date: April 29, 2021
    Inventors: Ting-Kuan LI, Syuan-Yi LIN, Sung-Feng TSAI, Wen-Chieh WANG, Su-Ying LU, Chia-Wen HSU
  • Patent number: 10473279
    Abstract: A wide-angle linear LED lighting device includes a polygonal lampshade, a base and at least two LED modules. The polygonal lampshade includes at least two lateral parts and an installation part. The base is disposed within the polygonal lampshade and disposed on an inner surface of the installation part. There is an included angle between the base and the inner surface of the installation part. The at least two LED modules are disposed on the base. The light beams emitted by the at least two LED modules are outputted from different lateral parts of the polygonal lampshade. The light-outputting characteristics of the wide-angle linear LED lighting device are correlated with the included angle and the at least two LED modules.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: November 12, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Ting Chien, Chia-Wen Hsu
  • Publication number: 20180209598
    Abstract: A wide-angle linear LED lighting device includes a polygonal lampshade, a base and at least two LED modules. The polygonal lampshade includes at least two lateral parts and an installation part. The base is disposed within the polygonal lampshade and disposed on an inner surface of the installation part. There is an included angle between the base and the inner surface of the installation part. The at least two LED modules are disposed on the base. The light beams emitted by the at least two LED modules are outputted from different lateral parts of the polygonal lampshade. The light-outputting characteristics of the wide-angle linear LED lighting device are correlated with the included angle and the at least two LED modules.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 26, 2018
    Inventors: Wei-Ting Chien, Chia-Wen Hsu
  • Patent number: 9908139
    Abstract: A timed glue gun includes a glue pushing unit including a trigger, a glue pushing member and a heating member for melting the hot melt glue stick, and a control unit including a timing member and an alarm member. The trigger is at a released position, and is operable to be pressed to a triggered position. The timing member starts to count upwards from zero when the heating member starts to heat up, and controls the alarm member to emit a first alarm signal when counting to a first elapsed time. The alarm member emits a second alarm signal when the timing member counts to a second elapsed time longer than the first elapsed time in response to continuous location of the trigger at the released position for the second elapsed time during heating of the heating member.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 6, 2018
    Inventor: Chia-Wen Hsu
  • Publication number: 20170128977
    Abstract: A timed glue gun includes a glue pushing unit including a trigger, a glue pushing member and a heating member for melting the hot melt glue stick ,and a control unit including a timing member and an alarm member. The trigger is at a released position, and is operable to be pressed to a triggered position. The timing member starts to count upwards from zero when the heating member starts to heat up, and controls the alarm member to emit a first alarm signal when counting to a first elapsed time. The alarm member emits a second alarm signal when the timing member counts to a second elapsed time longer than the first elapsed time in response to continuous location of the trigger at the released position for the second elapsed time during heating of the heating member.
    Type: Application
    Filed: April 18, 2016
    Publication date: May 11, 2017
    Inventor: Chia-Wen HSU
  • Patent number: 9352608
    Abstract: An electric pencil sharpener includes a cutter carrier, and first and second cutter members mounted on the cutter carrier and having long and short blade portions. The rear end of the short blade portion is disposed forwardly of the rear end of the long blade portion. A shaving space includes a rear region disposed between the rear ends of the long and short blade portions. The rear region allows extension of a tip portion of a pencil thereinto for pushing a switch actuation unit so as to deactivate a motor when the tip portion of the pencil has been sharpened to extend a predetermined length into the rear region.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: May 31, 2016
    Inventor: Chia-Wen Hsu
  • Patent number: 8721919
    Abstract: In one embodiment, an organic-inorganic metal oxide hybrid resin having the following formula: wherein each R1 is independently a substituted or non-substituted C1 to C10 alkyl group; each R2 is independently a substituted or non-substituted C1 to C10 alkyl group or benzyl group; n is a positive integer from 3 to 30; and each Y is independently (MO4/2)l[(MO)(4-a)/2M(OH)a/2]m[MO(4-b)/2M(OZ)b/2]p, wherein M is a metal; l is a positive integer from 10 to 90; m is a positive integer from 2 to 20; p is a positive integer from 4 to 15; a is a positive integer from 1 to 2; b is a positive integer from 1 to 2; and Z is an organosilane group.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: May 13, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Chen Huang, Wen-Bin Chen, Hsun-Tien Li, Chia-Wen Hsu
  • Publication number: 20130334458
    Abstract: In one embodiment, an organic-inorganic metal oxide hybrid resin having the following formula: wherein each R1 is independently a substituted or non-substituted C1 to C10 alkyl group; each R2 is independently a substituted or non-substituted C1 to C10 alkyl group or benzyl group; n is a positive integer from 3 to 30; and each Y is independently (MO4/2)l[(MO)(4-a)/2M(OH)a/2]m[MO(4-b)/2M(OZ)b/2]p, wherein M is a metal; l is a positive integer from 10 to 90; m is a positive integer from 2 to 20; p is a positive integer from 4 to 15; a is a positive integer from 1 to 2; b is a positive integer from 1 to 2; and Z is an organosilane group.
    Type: Application
    Filed: November 6, 2012
    Publication date: December 19, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Chen HUANG, Wen-Bin CHEN, Hsun-Tien LI, Chia-Wen HSU
  • Patent number: D1016283
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 27, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1022213
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu