Patents by Inventor Chia-Yang Chen
Chia-Yang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002845Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.Type: GrantFiled: January 13, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
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Publication number: 20240170415Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.Type: ApplicationFiled: April 11, 2023Publication date: May 23, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
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Publication number: 20240145403Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.Type: ApplicationFiled: February 6, 2023Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
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Publication number: 20240128376Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
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Publication number: 20240114688Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.Type: ApplicationFiled: November 21, 2022Publication date: April 4, 2024Applicant: United Microelectronics Corp.Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
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Publication number: 20240105795Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.Type: ApplicationFiled: February 16, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Ye Liu, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
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Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240071722Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
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Publication number: 20230360997Abstract: An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Siang-Yu Lin, Wen-Jung Tsai, Chia-Yang Chen, Chien-Cheng Lin
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Patent number: 11764162Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.Type: GrantFiled: August 19, 2020Date of Patent: September 19, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Chih-Wei Chen, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
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Patent number: 11749583Abstract: An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.Type: GrantFiled: July 19, 2021Date of Patent: September 5, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Siang-Yu Lin, Wen-Jung Tsai, Chia-Yang Chen, Chien-Cheng Lin
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Patent number: 11723144Abstract: An electronic device is provided, in which an antenna module for receiving and transmitting radiation signals is disposed on a mounting surface of a circuit board, and an inner layer of the circuit board is formed with a ground surface to arrange a strip-shaped ground circuit along the edges of the ground surface so that the ground circuit occupies at most 50% of the area of the ground surface to improve antenna radiation efficiency.Type: GrantFiled: September 2, 2021Date of Patent: August 8, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Chih-Wei Chen, Chien-Cheng Lin, Chao-Ya Yang, Chia-Yang Chen
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Publication number: 20230223322Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Ko-Wei Chang, Wen-Jung Tsai, Che-Wei Yu, Chia-Yang Chen
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Publication number: 20220375822Abstract: An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.Type: ApplicationFiled: July 19, 2021Publication date: November 24, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Siang-Yu Lin, Wen-Jung Tsai, Chia-Yang Chen, Chien-Cheng Lin
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Publication number: 20220225493Abstract: An electronic device is provided, in which an antenna module for receiving and transmitting radiation signals is disposed on a mounting surface of a circuit board, and an inner layer of the circuit board is formed with a ground surface to arrange a strip-shaped ground circuit along the edges of the ground surface so that the ground circuit occupies at most 50% of the area of the ground surface to improve antenna radiation efficiency.Type: ApplicationFiled: September 2, 2021Publication date: July 14, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Chih-Wei Chen, Chien-Cheng Lin, Chao-Ya Yang, Chia-Yang Chen
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Patent number: 11222852Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing an electronic component on a lower side of a first carrier and forming an encapsulant on an upper side of the first carrier. A first conductor is disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation. As such, the electronic package has a reduced thickness and improved antenna efficiency.Type: GrantFiled: September 17, 2019Date of Patent: January 11, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chih-Hsien Chiu, Chia-Yang Chen
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Publication number: 20210351097Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.Type: ApplicationFiled: April 27, 2021Publication date: November 11, 2021Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
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Patent number: 11069633Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.Type: GrantFiled: July 6, 2018Date of Patent: July 20, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ming-Fan Tsai, Chih-Hsien Chiu, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
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Publication number: 20210210435Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.Type: ApplicationFiled: August 19, 2020Publication date: July 8, 2021Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ming-Fan Tsai, Chih-Wei Chen, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
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Patent number: 10916526Abstract: A method for fabricating an electronic package includes providing a metal member including a supporting plate and a plurality of conductive pillars disposed on the supporting plate. A circuit structure is coupled to the conductive pillars. An electronic component is disposed on the metal member and electrically connected to the circuit structure. An encapsulant encapsulates the conductive pillars and the electronic component. Subsequently, the supporting plate is removed. Any mold can be used for fabricating the electronic package, no matter what the size of the electronic package is. Therefore, the fabricating cost of the electronic package is reduced.Type: GrantFiled: April 1, 2020Date of Patent: February 9, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chih-Hsien Chiu, Chia-Yang Chen, Chih-Chiang He