Patents by Inventor Chia-Yen Yeh

Chia-Yen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170207588
    Abstract: A micro coaxial RF connector applied to an audio processing unit includes a male connector with a connecting portion at an end, and the connecting portion has plural first screw threads, and the other end of the male connector is a transmission line, and a female connector is installed at a playing end of the audio processing unit, and the female connector has a groove, and plural second screw threads formed on the inner surface of the groove, configured to be corresponsive to the first screw threads, and electrically connected to the male connector. With the aforementioned locking and connecting method, the connector after many times of plugging and unplugging will not be loosened or damaged so easily, compared with the conventional insertion and flipping method, and the connector still maintains its original tightness after a long time of use, so as to maintain a stable sound quality.
    Type: Application
    Filed: October 11, 2016
    Publication date: July 20, 2017
    Inventor: Chia-Yen Yeh
  • Patent number: 7397717
    Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: July 8, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Han-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin
  • Publication number: 20060268642
    Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
    Type: Application
    Filed: May 26, 2005
    Publication date: November 30, 2006
    Inventors: Han-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin
  • Publication number: 20020121648
    Abstract: A double &dgr;-doped In0.34 Al0.66As0.85 Sb0.15/InP heterostructure field-effect transistor has been successfully grown by metalorganic chemical vapor deposition for the first time. Electron mobilities can be enhanced without sacrificing the carrier densities. A turn-on voltage as high as 1 V along with an extremely low gate reverse leakage current of 111 &mgr;A/mm at Vgs=−40V is achieved. The three-terminal on-and off-state breakdown voltages are as high as 40.8V and 16.1V, respectively. The output conductance is as low as 1.8 mS/mm even when the drain-to-source voltage is 15V. The gds is significantly smaller than that of our previously reported InAlAsSb/InGaAs/InP HFET. These characteristics are attributed to the use of the coupled &dgr;-doped structure, InP channel, In0.34 Al0.66As0.85 Sb0.15 Schottky layer, and to the large conduction-band discontinuity (&Dgr;Ec) at the InAlAsSb/InP heterojunction.
    Type: Application
    Filed: May 22, 2001
    Publication date: September 5, 2002
    Inventors: Wei-Chou Hsu, Yu-Shyan Lin, Chia-Yen Yeh, Yen-Wei Chen
  • Patent number: 6429468
    Abstract: A double &dgr;-doped In0.34 Al0.66As0.85 Sb0.15/InP heterostructure field-effect transistor has been successfully grown by metalorganic chemical vapor deposition for the first time. Electron mobilities can be enhanced without sacrificing the carrier densities. A turn-on voltage as high as 1 V along with an extremely low gate reverse leakage current of 111 &mgr;A/mm at Vgs=−40V is achieved. The three-terminal on-and off-state breakdown voltages are as high as 40.8V and 16.1V,respectively. The output conductance is as low as 1.8 mS/mm even when the drain-to-source voltage is 15V. The gds is significantly smaller than that of our previously reported InAlAsSb/InGaAs/InP HFET. These characteristics are attributed to the use of the coupled &dgr;-doped structure, InP channel, In0.34 Al0.66As0.85 Sb0.15 Schottky layer'and to the large conduction-band discontinuity(&Dgr;Ec) at the InAlAsSb/InP heterojunction.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: August 6, 2002
    Assignee: National Science Council
    Inventors: Wei-Chou Hsu, Yu-Shyan Lin, Chia-Yen Yeh